• 제목/요약/키워드: clock

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낸드 플래시 메모리를 위한 CLOCK 알고리즘 기반의 효율적인 버퍼 교체 전략 (An Efficient Buffer Replacement Policy based on CLOCK Algorithm for NAND Flash Memory)

  • 김종선;손진현;이동호
    • 정보처리학회논문지D
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    • 제16D권6호
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    • pp.825-834
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    • 2009
  • 최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

An I/O Bus-Based Dual Active Fault Tolerant Architecture fort Good System Performance

  • Kwak, Seung-Uk;Kim, Jeong-Il;Jeong, Keun-Won;Park, Kyong-Bae;Kang, Kyong-In;Kim, Hyen-Uk;Lee, Kwang-Bae
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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    • pp.515-520
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    • 1998
  • In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

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Reciprocal Control of the Circadian Clock and Cellular Redox State - a Critical Appraisal

  • Putker, Marrit;O'Neill, John Stuart
    • Molecules and Cells
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    • 제39권1호
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    • pp.6-19
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    • 2016
  • Redox signalling comprises the biology of molecular signal transduction mediated by reactive oxygen (or nitrogen) species. By specific and reversible oxidation of redoxsensitive cysteines, many biological processes sense and respond to signals from the intracellular redox environment. Redox signals are therefore important regulators of cellular homeostasis. Recently, it has become apparent that the cellular redox state oscillates in vivo and in vitro, with a period of about one day (circadian). Circadian timekeeping allows cells and organisms to adapt their biology to resonate with the 24-hour cycle of day/night. The importance of this innate biological timekeeping is illustrated by the association of clock disruption with the early onset of several diseases (e.g. type II diabetes, stroke and several forms of cancer). Circadian regulation of cellular redox balance suggests potentially two distinct roles for redox signalling in relation to the cellular clock: one where it is regulated by the clock, and one where it regulates the clock. Here, we introduce the concepts of redox signalling and cellular timekeeping, and then critically appraise the evidence for the reciprocal regulation between cellular redox state and the circadian clock. We conclude there is a substantial body of evidence supporting circadian regulation of cellular redox state, but that it would be premature to conclude that the converse is also true. We therefore propose some approaches that might yield more insight into redox control of cellular timekeeping.

Investigation of gene-gene interactions of clock genes for chronotype in a healthy Korean population

  • Park, Mira;Kim, Soon Ae;Shin, Jieun;Joo, Eun-Jeong
    • Genomics & Informatics
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    • 제18권4호
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    • pp.38.1-38.9
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    • 2020
  • Chronotype is an important moderator of psychiatric illnesses, which seems to be controlled in some part by genetic factors. Clock genes are the most relevant genes for chronotype. In addition to the roles of individual genes, gene-gene interactions of clock genes substantially contribute to chronotype. We investigated genetic associations and gene-gene interactions of the clock genes BHLHB2, CLOCK, CSNK1E, NR1D1, PER1, PER2, PER3, and TIMELESS for chronotype in 1,293 healthy Korean individuals. Regression analysis was conducted to find associations between single nucleotide polymorphism (SNP) and chronotype. For gene-gene interaction analyses, the quantitative multifactor dimensionality reduction (QMDR) method, a nonparametric model-free method for quantitative phenotypes, were performed. No individual SNP or haplotype showed a significant association with chronotype by both regression analysis and single-locus model of QMDR. QMDR analysis identified NR1D1 rs2314339 and TIMELESS rs4630333 as the best SNP pairs among two-locus interaction models associated with chronotype (cross-validation consistency [CVC] = 8/10, p = 0.041). For the three-locus interaction model, the SNP combination of NR1D1 rs2314339, TIMELESS rs4630333, and PER3 rs228669 showed the best results (CVC = 4/10, p < 0.001). However, because the mean differences between genotype combinations were minor, the clinical roles of clock gene interactions are unlikely to be critical.

후성유전학 시계를 통해 감지될 수 있는 양극성 장애의 메틸화 변화 (Methylation Changes in Bipolar Disorder that can be detected through The Epigenetic Clock)

  • 정연오;조광원
    • 통합자연과학논문집
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    • 제16권3호
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    • pp.75-80
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    • 2023
  • Bipolar disorder is a mental illness characterized by extreme mood and behavioral swings, such as highs of euphoria and lows of depression. It is a socially significant disorder in which people with the disorder experience intense mood swings and, for those with severe bipolar disorder, it is even difficult leading a normal life. High stress levels in people with mental illness can lead to neuroendocrine disruption, and it is strongly linked to aging. When the neuroendocrine system becomes vulnerable to these mental illnesses and stress, it is likely to accelerate aging. And it's the epigenetic clock that can measure the extent of this accelerated aging. The Epi clock, a pan tissue clock, measures aging through DNA methylation, and the degree of methylation is modified and changed by environmental conditions in the body. Therefore we wanted to check the changes in the epigenetic age of the patients with bipolar disorder. While we found no significant differences in epigenetic age, we did confirm the possibility that people with bipolar disorder have different methylation than normal people. We also found that the EPIC array data fit better on the Epi clock than on the Horvath clock with age-accelerated data from normal people.

히스톤 3 아세틸화(H3Ac)를 통한 De-Etiolated 1 (DET1)의 애기장대 생체시계 조절 (Regulation of Arabidopsis Circadian Clock by De-Etiolated 1 (DET1) Possibly via Histone 3 Acetylation (H3Ac))

  • 송해룡
    • 생명과학회지
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    • 제22권8호
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    • pp.999-1008
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    • 2012
  • 자기 현가적(self-sustaining) 조절 장치인 생체시계는 24시간 주기의 생체리듬을 조절하며 또한 생물체로 하여금 매일 변화하는 자연환경의 외부 신호를 인지할 수 있도록 해준다. 생체시계 유전자의 발현 조절은 전사/해독의 역환류 기작을 통해 이루어진다. 애기장대 LATE ELONGATED HYPOCOTYL (LHY)와 CIRCADIAN CLOCK-ASSOCIATED 1 (CCA1)는 아침에 최고조로 발현되며 해독된 LHY and CCA1는 저녁에 최고로 발현되는 TIMING OF CAB EXPRESSION1 (TOC1)의 발현을 억제한다. TOC1단백질은 LHY와 CCA1 발현을 촉진시킴으로써 생체시계의 핵심 진자(oscillator)를 형성한다. 동물에서 생체시계의 주요 전사 인자인CLOCK은 아세틸화효소 활성 기능을 가지며, 이는 생체시계의 기능 유지에 아세틸화의 중요함을 의미한다. 하지만 애기장대 생체시계에 아세틸화를 담당하는 인자에 대한 정보는 현재 보고된 바가 없다. 본 연구에서 DET1 (De-Etiolated1)는 암조건하에서 애기장대 생체시계 관련 핵심인자 중 하나인 LHY발현을 억제하는데 필요하며 이의 억제는 H3Ac 조절을 통해 이루어짐을 증명하였다. 하지만 LHY 아세틸화를 담당하는 효소의 발굴 및 이들 효소와 DET1과의 연결을 찾는 문제는 여전히 미재로 남아있다.

1 Gb/s gated-oscillator burst mode CDR for half-rate clock recovery

  • Han, Pyung-Su;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권4호
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    • pp.275-279
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    • 2004
  • A new burst mode clock and data recovery circuit is realized that improves the previousldy-known gated-oscilletor technique with half rate clock recovery, The circuit was fabricated with 0.25um CMOS technology, and its functions were confirmed up to 1 Gbps.

클럭-피드쓰루를 개선한 새로운 전류 기억 소자 (New current memory cell with clock-feedthrough reduction scheme)

  • 민병무;김재완;김수원
    • 전자공학회논문지D
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    • 제34D권1호
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    • pp.30-34
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    • 1997
  • An improved clock-feedthrough compensation scheme for switche dcurrent system is proposed. Both the signal dependent and the constant clock-feedthrough terms are cancelled by using both NMOS and PMOS current samplers and by adopting a source replication technique. The proposed current memory cell was fabricated with 0.6$\mu$m CMOS process. Both experimental and theoretical results on clock-feedthrough error reveal substantial reduction over the existing compensation schemes.

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CAN 시간동기를 이용한 복수 전동기 동기제어 (Synchronization Control of Multiple Motors using CAN Clock Synchronization)

  • ;서영수
    • 제어로봇시스템학회논문지
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    • 제14권7호
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    • pp.624-628
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    • 2008
  • This paper is concerned with multiple motor control using a distributed network control method. Speed and position of multiple motors are synchronized using clock synchronized distributed controllers. CAN (controller area network) is used and a new clock synchronization algorithm is proposed and implemented. To verify the proposed control algorithm, two disks which are attached on two motor shafts are controlled to rotate at the same speed and phase angle with the same time base using network clocks.

Vernier 방법을 이용한 Low-jitter DLL 구현 (Design of Low-jilter DLL using Vernier Method)

  • 서승영;장일권;곽계달
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.83-86
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    • 2000
  • This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

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