• The Journal of Korean Institute for Practical Engineering Education
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• v.4 no.2
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• pp.129-135
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• 2012

There are many ways in which electric vehicles are mathematically modeled and simulated. The components have different physical background and models, but have to fit into one mathematical model. A multiphysics model structure is required. Depending on the goal of the simulation, there are various levels on which the simulation can be performed. This is called multilevel, consisting of a conceptual system level, a circuit level and a more detailed component level. This paper discusses which multiphysics models and multilevel simulations are required for the various components in an electric vehicle. Also, this simulation approach could improve the effectiveness of learning in engineering education.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.4
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• pp.748-755
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• 2009

This paper proposes a 18-step back-to-back voltage source converter using four sets of 3-Level converter module with auxiliary circuit to increase the number of steps. The proposed back-to-back voltage source converter has an independent control capability of active power and reactive power at the interconnected ac system. The operational feasibility of proposed system was verified through computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was verified through experimental results with a scaled hardware model. The proposed back-to-back converter can be widely applied for interconnecting the renewable energy source to the power grid.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.11-19
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• 2010

Register transfer level power macromodeling is well known as a promising technique for accurate and efficient power estimation. This paper proposes effective approaches based on the tablebased method for the RTL power macro-modeling. The new parameter SD, which characterizes the distribution of switching activities for each gate in the circuit, is one of the contributions. The new parameter SD has strong correlation with power consumption. We also propose an accurate table reference method considering the circuit characteristics. The table reference method is applicable for every table-based method and outputs more accurate power value. The experimental results show that the combination of the proposed methods reduces max error 30.36% in the best case, comparing conventional methods. The RMS error is also improved 1.70% in the best case.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.823-828
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• 2011

We have systematically designed and experimentally demonstrated the opto-electrical predistortion optical transmitter using microwave circuit modelling for reducing the nonlinearity of the distributed-feedback laser diode (DFD-LD). The DFB-LD is analyzed using microwave circuits model based on rate equations. Through the system-level simulation for predistortion method, the optimized characteristics of the RF components in the system are confirmed. The simulated and experimental results show the reduced distortion products. These results are analyzed as the evaluation parameters for the miniaturization and optimization of the opto-electrical predistortion method in radio-over-fiber systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.277-278
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• 2005

Admittance Spectroscopic analysis was applied to study the effect of LiF buffer layer and to model the equivalent circuit for poly(2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene) (MEH-PPV)-based polymer light emitting diodes (PLEDs) with the LiF cathode buffer layer. The single layer device with ITO/MEH-PPV/Al structure can be modeled as a simple parallel combination of resistor and capacitor. Insertion of a LiF layer at the Al/MEH-PPV interface shifts the highest occupied molecular orbital level and the vacuum level of the MEH-PPV layer as a result the barrier height for electron injection at the Al/MEH-PPV interface is reduced. The admittance spectroscopy measurement of the devices with the LiF cathode buffer layer shows reduction in contact resistance ($R_c$), parallel resistance ($R_p$) and increment in parallel capacitance ($C_p$).

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1346-1354
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• 2018

Quality of the power system depends upon the reliability of its components such as transformer, transmission lines, insulators, circuit breakers and isolators. The transient voltage due to internal or external reasons may affect the insulation level of the components. The insulation level of these components must be tested against these conditions. Different studies, testing of different electrical components against high voltage impulses and different industrial applications rely on the international manufactures for pulsed power generation and testing, that is quite expensive and large in size. In this paper a model of impulse voltage generator with capacitive load of pin type insulator is studied by simulation method and by an experimental setup. A ten stage high voltage impulse generator (HVIG) is designed and implemented for different applications. In this proposed model, the cost has been reduced by using small and cheap capacitors as an alternative for large and expensive ones while achieving the same effectiveness. Effect of the distributed capacitance in each stage is analyzed to prove the effectiveness of the model. Different values of front and tail resistances have been used to get IEC standard waveforms. Results reveal the effectiveness at reduced cost of the proposed model.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1642-1649
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• 2018

A single-stage flyback LED AC-DC converter based on primary-side control under constant current mode is proposed in this study. The proposed converter features low total harmonic distortion (THD) and high power factor (PF). It also consists of a zero-crossing distortion compensation circuit and a variable duty ratio control compensation circuit to deal with the line current distortions caused by fixed duty ratio control. The system model and layout are built in Simplis and Cadence, respectively. The feasibility and performance of the proposed circuit is verified by designing and fabricating an IC controller in the HHNEC $0.35{\mu}m$ 5 V/40 V HVCMOS process. Experimental results show that the PF can reach a level in the range of 0.985-0.9965. Moreover, the average THD of the entire system is approximately 10%, with the minimum being 6.305%, as the input line voltage changes from 85 VAC to 265 VAC.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.63-66
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• 1996

An micro model for the power insulated Gate Bipolar Transistor(IGBT) is developed. The model consistently described the IGBT steady-state current-voltage characteristics and switching transient current and voltage waveform for all loading conditions. The model is based on the equivalent circuit of a MOSFET with supplies the base current to a low-gain, high-level injection, bipolar transistor with its base virtual contact at the collector and of the base. Model results are compared with measured turn-on and turn-off waveform for different drive, load, and feedback circuits.