• Structural Engineering and Mechanics
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• v.62 no.6
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• pp.675-693
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• 2017

In this paper, based on the first-order shear deformation plate theory, buckling analysis of piezoelectric coupled transversely isotropic rectangular plates is investigated. By assuming the transverse distribution of electric potential to be a combination of a parabolic and a linear function of thickness coordinate, the equilibrium equations for buckling analysis of plate with surface bonded piezoelectric layers are established. The Maxwell's equation and all boundary conditions including the conditions on the top and bottom surfaces of the plate for closed and open circuited are satisfied. The analytical solution is obtained for Levy type of boundary conditions. The accurate buckling load of laminated plate is presented for both open and closed circuit conditions. From the numerical results it is found that, the critical buckling load for open circuit is more than that of closed circuit in all boundary and loading conditions. Furthermore, the critical buckling loads and the buckling mode number increase by increasing the thickness of piezoelectric layers for both open and closed circuit conditions.

• 전기의세계
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• v.22 no.1
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• pp.42-51
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• 1973

The contriving equivalent circuit of single phase induction motor which does not separate the primary leakage reactance and the secondary leakage reactance by the revolving field theory, and the graphically calculating method of the characteristics with T-type circle diagram of three phase induction motor which does not suppose the primary leakage reactance can be drawn up only by the no load test, the lock test, and measuring the resistance of stator winding are suggested in this paper. The method which can calculate the parameters of the equivalent circuit and the characteristics with no load test, lock test and measuring resistance of stator windings is suggested in this paper. Considered the exciting current in lock test, we could calculate very accurate characteristics of the single phase induction motor.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.38-40
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• 2002

A study on the test method and the test facilities of synthetic capacitive current tests have been very slight and the direct test method with the short-circuit generator and power transformer only used up to now. However, according to the development of analysis technique of power system and design and manufacture technique we are realized that direct testing method is not satisfactory to evaluate the performance of circuit-breaker because it is difficult to simulate precisely the conditions of power system. Therefore, in order to solve these problem this paper deals with the tests methods and the design technique of the tests facilities of the synthetic capacitive current based on the same theory with the synthetic short-circuit tests.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.1
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• pp.57-65
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• 2016

This paper was analyzed the characteristics of piezoelectric inkjet print head using finite element method(FEM). It showed the bending node driving of piezoelectric and relation theory principle consider piezoelectric material characteristics and ink characteristics. From such result we were had the piezoelectric head design and manufacture. It got a this head characteristics through experiment, we confirmed that proper voltage control is possible to through ink drop control experiment of piezoelectric print head. This paper was obtained the suitable ink jetting characteristics that manufacture the control circuit and piezoelectric inkjet print head. This practice product was applied to improvement of PCB electric circuit pattern by etching resist ink that PCB manufactured to complex process over traditional 6 stages can be simpled to 1 stage by inkjet printing technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

• Structural Engineering and Mechanics
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• v.60 no.2
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• pp.271-299
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• 2016

In this article, based on the higher-order shear deformation plate theory, buckling analysis of a rectangular plate made of functionally graded piezoelectric materials and its effective parameters are investigated. Assuming the transverse distribution of electric potential to be a combination of a parabolic and a linear function of thickness coordinate, the equilibrium equations for the buckling analysis of an FGP rectangular plate are established. In addition to the Maxwell equation, all boundary conditions including the conditions on the top and bottom surfaces of the plate for closed and open circuited are satisfied. Considering double sine solution (Navier solution) for displacement field and electric potential, an analytical solution is obtained for full simply supported boundary conditions. The accurate buckling load of FGP plate is presented for both open and closed circuit conditions. It is found that the critical buckling load for open circuit is more than that of closed circuit in all loading conditions. Furthermore, it is observed that the influence of dielectric constants on the critical buckling load is more than those of others.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.203-206
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• 2000

In this paper, we discuss an efficient steady-state analysis of reactance oscillators having multiple oscillations. Our oscillator is consisted of the Cauer or Foster reactance sub-circuit and a negative resistor such as tunnel diode. The reactance circuit has many resonance and antiresonance points on the frequency response curve. Such a circuit having the specified resonance and anti-resonance points can be easily synthesized with the fundamental circuit theory. In this case, the multiple oscillations may occur near at the anti-resonance points. We have developed a user friendly simulator for getting the exact steady state responses using the SPICE.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.546-547
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• 2013

This paper proposes an arc fault circuit interrupter (AFCI) using the distorted voltage wave in electric arc faults. It perceives a voltage instantaneously at the time of voltage drop. and occurrence. It is an AFCI of the new concept which operates with high reliability. The primary reason of electric fire is arc and spark. It prevents an electric fire or an electric leakage accident with quick responsiveness. Earth Leakage Circuit Breaker(ELB), Molded_case Circuit Breaker (MCCB) or Residual Current Protective Device(RCD) can not cut off electric arc or spark to be a major factor of electrical fire. This theory will be able to intercept an arc or a spark. which occurrence with periodic. Consequently It raises a reliability and validates a practicality of RCD.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.2
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• pp.93-99
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• 2001

A new type geometric and mathematical network reduction model is introduced. Large-scale network is analyzed with analytic approach. The graph has many nodes, branches and loops. Circuit equation are obtained from these elements and connection rule. In this paper, the analytic relation between voltage source has a mutual different graphic property. Node-reduction procedure is achieved with this circuit property. Consequently voltage source value is included into the adjacent node-analyzing equation. A resultant model equations are reduced as much as voltage source number. Matrix rank is (n-1-k), where n, k is node and voltage source number. The reduction procedure is described and verified with geometric principle and circuit theory. Matrix type circuit equation can be composed with this technique. The last results shall be calculated by using computer.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.874-875
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• 2007

This paper introduces major potential faults of IPMSM and their simulation realization methods. The faults of IPMSM, generally, contain single-phase open circuit, single-phase or 3-phase short circuit, and uncontrolled generation. When different fault occurs, the circuit of total system including motor and inverter also will be changed. Therefore, it is necessary to analyze and establish independent model for each kind of fault. In this paper, first, the drive circuit is analyzed as different fault type. Then, the corresponding simulation results solved in Simulink@MATLAB are given. The absence of experiment results leads that the veracity of simulation results can not be verified, but the tendency will be explained by theory analysis.