• Journal of Power Electronics
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• 제18권3호
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• pp.802-816
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• 2018

A digital direct phase-shift control (DDPSC) method based on the phase-shifted full-bridge LLC (PSFB-LLC) converter is presented. This work combines DDPSC with the conventional linear control to obtain a hybrid control strategy that has the advantages of linear control and DDPSC control. The strategy is easy to realize and has good dynamic responses. The PSFB-LLC circuit structure is simple and works in the fixed frequency mode, which is beneficial to magnetic component design; it can realize the ZVS of the switch and the ZCS of the rectifier diode in a wide load range. In this work, the PSFB-LLC converter resonator is analyzed in detail, and the concrete realization scheme of the hybrid control strategy is provided by analyzing the state-plane trajectory and the time-domain model. Finally, a 3 kW prototype is developed, and the feasibility and effectiveness of the DDPSC controller and the hybrid strategy are verified by experimental results.

• 디지털산업정보학회논문지
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• 제12권2호
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권7호
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• pp.335-342
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• 2003

This paper presents a forward type high voltage pulse power supply for high voltage small current, which can be designed as a simple circuit configuration and managed easily using Power-MOSFET in the view of commercialization. According to the switching frequency, coupling factor(k) and duty ratio(D), the Principle of basic operation and the characteristics of the proposed pulse power supply are estimated. Simulation results have demonstrated the feasibility of the proposed pulse power supply. Also experimental results are presented to verify theoretical discussion with a lamp type ozonizer as a load. For studying the application at the part of environment of water, When ozonizer gas reacts with a colon bacillus, the sterilization characteristics of a colon bacillus according to the ozone concentration and response time have been investigated. This proposed pulse power supply will be able to be practically used as a pulse power supply in various environment improvement facilities like sterilization of colon bacillus, deodorization, and Nox gas elimination.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 E
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• pp.1675-1677
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• 1998

It is currently increasing to use surge protection devices in the protection of various electronic circuits from the transient overvoltages such as lightning strikes and switching surges. For this reason, the simulation methods, which can easily predict the protection performance of the devices, are strongly required in order to design the adequate surge protection circuits in lightning surge cut-off performance and economic aspects. This paper deals with ZnO varistor modeling method for designing a surge protection circuit and suggests the Pspice simulation model which takes the characteristic of varying clamping voltage into consideration during the time-to-crest, in range of $8{\sim}30{\mu}s$, of surge current applied to a ZnO varistor. The ZnO varistor Pspice simulation data introduced in this paper has produced almost same values as the measured results experimentally.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.160-163
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• 2004

A passive lossless turn-on/turn-off snubber network is proposed for the boost PWM converter. Previous AC/DC PFC Boost Converter perceives feed forward signal of output for average current-mode control. Previous Boost Convertor, the Quantity of input current will be decreased by the decrease of output current in light load, and also Power factor comes to be decreased. Also the efficiency of converter will be decreased by the decrease of power factor. The proposed converter presents the good PFC, low line current harmonic distortions and tight output voltage regulations using energy recovery circuit. All of the semiconductor devices in the converter are turned on under exact or near zero voltage switching(ZVS). No additional voltage and current stresses on the main switch and main diode occur. To show the superiority of this converter is verified through the experiment with a 640W, 100kHz prototype converter.

• Journal of Magnetics
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• 제19권2호
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• pp.197-204
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• 2014

A transcranial magnetic stimulation device is a complicated appliance that employs a switching power device designed for discharging and charging a capacitor to more than 1 kV. For a simple transcranial magnetic stimulation device, this study used commercial power and controlled the firing angle using a Triac power device. AC 220V 60 Hz, the power device was used directly on the tanscranial magnetic stimulation device. The power supply device does not require a current limiting resistance in the rectifying device, energy storage capacitor or discharge circuit. To control the output power of the tanscranial magnetic stimulation device, the pulse repetition rate was regulated at 60 Hz. The change trigger of the Triac gate could be varied from $45^{\circ}$ to $135^{\circ}$. The AVR 182 (Zero Cross Detector) Chip and AVR one chip microprocessor could control the gate signal of the Triac precisely. The stimulation frequency of 50 Hz could be implemented when the initial charging voltage Vi was 1,000 V. The amplitude, pulse duration, frequency stimulation, train duration and power consumption was 0.1-2.2T, $250{\sim}300{\mu}s$, 0.1-60 Hz, 1-100 Sec and < 1 kW, respectively. Based on the results of this study, TMS can be an effective method of treating dysfunction and improving function of brain cells in brain damage caused by ischemia.

• 반도체디스플레이기술학회지
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• 제3권1호
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• pp.21-26
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• 2004

Recently with the development of power switching device and DSP which has peripheral devices to control AC servo system, the servo technology has met a new development opportunity. Those things make it possible to reduce the time of developing a AC servo system. Fixed point DSP such as TMS320F240x, and TMS320F28x series have a disadvantage in calculating floating number where TMS320C32 or TMS320C31 are floating point DSP. However they usually become a complex hardware system to implement the AC servo system and it increases the cost. In this study, a DSP based AC servo system with a 3-phase PMSM is proposed. The newly produced DSP TMX320F28l2-version C which has the performance of fast speed, 150MIPS, and a rich peripheral interface such as a 12bit high speed AD converter, QEP(Quadrature Encoder Pulse) circuit, PDPINT(Power Drive Protect Interrupt), SVPWM module and dead time module are used. This paper presents a method to overcome fixed point calculating using scaling all parameters. Also space vector pulse width modulation (SVPWM) using off-set voltage and a digital PI control are implemented to the servo system.

• 디지털산업정보학회논문지
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• 제10권1호
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1577-1579
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• 1994

200-MW pulse modulators(total 11units) for the PLS linac employ the SCR phase control circuit. It controls 3-phase AC line voltage for the high-voltage DC power supply (DCPS, maximum of 25kVDC, 4.2A) which charges the pulse forming network(PFN). The PFN delivers 400kV, 500A, ESW $7.5{\mu}s$ pulse power to the 80-MW klystron amplifier tube. The SCR regulates 3-phase AC power and feeds to the high voltage transformer. Two different types of the transformer configurations namely ${\Delta}-{\Delta}$ and ${\Delta}-Y$, are alternatively installed to 11 modulator units for the suppression of harmonic noises. RC filters and reactors are also installed. Currently, approximately 110-kW of average AC power per unit is consumed at the normal operation level of the modulator with 30pps. This paper presents the operational characteristics of the high power pulse modulator, especially the experimental results of the AC line harmonic components generated by the operation of the high power pulse modulator to suppress the switching noises from the SCR and rectifying diode arrays.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권3호
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• pp.372-378
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• 2012

This paper deals with a 3-phase voltage disturbance generator for a performance test of custom power devices such as dynamic voltage restorers (DVR), dynamic uninterruptable power supplies (UPS), etc. The operating principle of the proposed circuit is described in each mode of voltage sag, swell, outage, and unbalance. The main components of the proposed disturbance generator are silicone controlled rectifier (SCR) thyristors, variable autotransformers, and transformers. Therefore, the disturbance generator can be implemented with a considerably low cost compared to the conventional pulse width modified (PWM) inverter and converter type generators. Furthermore, it has good features of high reliability with simple structure, high efficiency caused by no PWM switching of the SCR thyristors, and easy control with a wide variation range. To verify the validity of the proposed scheme, simulations and experiments are carried out.