• 자원ㆍ환경경제연구
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• 제31권4호
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• pp.571-595
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• 2022

본 연구는 신규 발전기 진입에 따라 기존사업자들이 차단기를 교체해야 하는 경우 발생하는 교체비용 분담을 이론적으로 분석한다. 협조게임이론의 비용배분 문제에 널리 쓰이는 순차적 균등기여규칙을 비용배분 규칙으로 채택하고 몇 가지 기준에 따라 다양한 비용배분 안을 도출한 후 각 대안이 바람직한 여러 공리들을 얼마나 충족시키는지 조사한다. 분석에 따르면 (i) 신규사업자의 비용, 잔존가치, 망운영자를 제외하는 안과 (ii) 신규사업자의 비용과 잔존가치는 제외하고 망운영자는 포함하는 안이 다른 안들에 비해 상대적으로 우수한 것으로 나타난다. 또한 현실적 요인을 고려하여 현실성이 높은 배분안을 찾고 그 공리적 특성을 분석한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.93-96
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• 2003

Korea Multi-Purpose SATellite (KOMPSAT) uses software-controlled unregulated bus system In which the main bus is directly connected to a battery and the duty-ratio for PWM switch is generated by the on-board satellite software algorithm. In this paper, we propose a new power-stage circuit that can be available for modularization of a solar array regulator(SAR) which is used in the KOMPSAT. The operations at each mode and current sharing characteristics of the power-stage are analyzed and verified by simulation and experiments on a prototype converter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.451-455
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• 1991

The PWM control technique is proposed which can eliminate the harmonic components of the nonsinusoidal ac line current such as the current of 6-phase rectifier by injecting PWM current. TSC(Time-Sharing Control) is adopted to avoid the unbalance between three PWM injection currents at the three-phase system. Also a new power circuit for three-phase filter is suggested for realizing the proposed PWM control technique. The operation characteristics are investigated theoretically and experimentally to show the feasibility of the optimized injection method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.432-434
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• 1994

This paper describes a phase-shifter which can flexibly adjust the active and reactive power flow through an ac transmission line. The phase-shifter has two voltage-source converters sharing an energy storage capacitor. The magnitude of the injected voltage is controlled by the converter I connected in parallel with the sending terminal, while that of phase angle by the converter II in series with the line through the coupling transformer. In order to analyze the whole system operation, an equivalent circuit model was developed and verified by a computer simulation with EMTP code.

• 전기학회논문지
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• 제60권5호
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• pp.971-976
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• 2011

This paper proposes a test system for a valve and poles building blocks used for large scale inverters such as STATCOM, SSSC, UPFC and VSC HVDC. Power semiconductors in the valve are normally connected in series to withstand switching voltage much larger than the voltage rating of a single power semiconductor. Therefore, there is a need to verify if the dynamic voltage sharing during switching in a valve is satisfactory. In this paper, we propose a test system that provides the necessary test condition: voltage and current in the valve using resonant circuits. A test scheme for a single phase inverter consisting two poles is also proposed. The performance of the inverter pole has to be verified at the factory test, before the system is installed at the site to secure the reliability of the system. The proposed scheme makes it possible to confirm if the pole can withstand voltage and current switching condition and handle loss.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.313-316
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• 2002

A SRM inverter has very low switching frequency. This results in reducing the burden for a high-speed of the gate-amp interface circuit. and the linearity of optocoupler is used to protect the intanteneous peak current for the stable operation In this paper, series resistor is used to equal the current sharing of each switching device and a linear gate-amp is proposed to protect the intanteneous peak current which occurs in transient state.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.176-181
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employs active and reactive power control of frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel-connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employees an instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Furthermore, the proposed control scheme is verified through the experiment in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Journal of Power Electronics
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• 제12권2호
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• pp.258-267
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• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• 대한전기학회논문지
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• 제39권2호
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• pp.157-163
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• 1990

The PWM inverter investigated in this paper utilizes a bridge type current sharing reactor circuit with tow pairs of complementary transistor at each phase. The driving signals for this inverter are 3 level PWM waves of W type an M type modulation, which are obtained from a microprocessor based on the switching time data obtained by switching position calculation of triangular and sine modulation wave. The output voltage waveforms of this inverter have 5 level phase voltage and 9 level line voltage of PWM. The harmonics of the output voltage are reduced to half when it is compared with single CTI, and the occurrence of harmonics is also reduced.

• 전자공학회논문지A
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• 제32A권2호
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• pp.140-150
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• 1995

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.