• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.6
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• pp.359-367
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• 2004

The switched reluctance motor(SRM) has considerable potential for industrial applications because of its high result lily as a result of the absence of rotor windings. In some applications with SRM, paralleling strategy is often used for cost saving, increasing of current capacity and system reliability. A SRM inverter has very low ,switching frequency. This results in reducing the burden for a high-speed of the gate-amp interface circuit. and the linearity of optocoupler is used to protect the instantaneous peak current for the stable operation. In this paper, series resistor is used to equal the current sharing of each switching device and a linear gate-amp is proposed to protect the instantaneous peak current which occurs in transient state. The proposed paralleling strategy is verified by experimental results.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.3
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• pp.77-83
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• 2008

In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1356-1361
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• 2008

A switched reluctance generator(SRG) has simple magnetic structure, and needs simple power electronic driving circuit. But, a SRG are no windings or permanent magnets on the rotor, and there are concentrated windings placed around each salient pole on the stator. Because of the characteristics of time-sharing excitation, the control of SRG is very flexible. And there are several parameters for controlling SRG, such as switch turn-on angle, switch turn-off angle, and exciting voltage and controlling mode, all these will affect the generation greatly. A SRG has positive torque at increasing inductance region and negative torque at decreasing inductance region. In this paper, we studied characteristics about the switch turn-on and off angles according to switch method for constant output voltage of the fixed speed SRG. It is the acoustic noise and torque ripple characteristics. Characteristics for a switch angle and method are presented by experiment using a 50W SRG with 12/8 poles.

• Journal of the Korea Society for Simulation
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• v.10 no.3
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• pp.59-70
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• 2001

Typical low-level image processing tasks require thousands of operations per pixel for each input image. Traditional general-purpose computers are not capable of performing such tasks in real time. Yet important features of traditional computers are not exploited by low-level image processing tasks. Since storage requirements are limited to a small number of low-precision integer values per pixel, large hierarchical memory systems are not necessary. The mismatch between the demands of low-level image processing tasks and the characteristics of conventional computers motivates investigation of alternative architectures. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. In this paper we implemented various image processing filtering using the format converter. Also, we realized from conventional gray image process to color image process. This design method is based on realized the large processor-per-pixel array by integrated circuit technology This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.331-336
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• 2008

Magnetic path direction in the back-iron of a linear induction motor(LIM) is perpendicular to that of the lift-magnet of the MAGLEV which is recently developing in KOREA. In general the back-iron is isolated magnetically in conventional rail in order to eliminate the thrust dependency of the LIM on the lift force. However the magnetic isolation causes some increase in construction and management cost. So a unit-type rail system is considered, which the magnetic circuit of the back-iron is sharing that of the lift-magnet. In this paper 3-dimensional analysis for the lift-magnet is carried out using finite element method. As a result, a new shape of the unit-type rail is presented to reduce the magnetic dependency between thrust force and lift force. Also the distribution of magnetic flux density vectors and current-lift force characteristics are presented.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.36-38
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• 2018

As the battery capacity requirement increases, battery cells are connected in a parallel configuration. However, the sharing current of each battery cell becomes unequal due to the imbalance between cell's impedance which results the mismatched states of charge (SOC). The conventional fixed-resistance balancing methods have a limitation in battery equalization performance and system efficiency. This paper proposes a battery equalization method based on dynamic resistance technique, which can improve equalization performance and reduce the loss dissipation. Based on the SOC rate of parallel connected battery cells, the switches in the equalization circuit are controlled to change the equivalent series impedance of the parallel branch, which regulates the current flow to maximize SOC utilization. To verify the method, operations of 4 parallel-connected 18650 Li-ion battery cells with 3.7V-2.6Ah individually are simulated on Matlab/Simulink. The results show that the SOCs are balanced within 1% difference with less power dissipation over the conventional method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1542-1547
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• 2012

Asynchronous phenomenon occurs on the synchronous generators under power system when a generator's amplitude of electromagnetic force, phase angle, frequency and waveform etc become different from those of other synchronous generators which can follow instantly varying speed of turbine. Because the amplitude of electromagnetic force, phase frequency and waveform differ from those of other generators with which are to be put into parallel operation due to the change of excitation condition for load sharing and the sharing load change, if reactive current in the internal circuit circulates among generators, the efficiency varies and the stator winding of generators are overheated by resistance loss. When calculation method of protection settings and logic for protection of generator asynchronization will be recommended, a distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome asynchronizing protection, this paper describes an improved backup protection coordination scheme using a new logic that will be suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2059-2066
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• 2001

In this paper, we proposed a method to reduce the number of input pins in one-dimensional VLSI array for fractal image compression. We use quad-tree partition scheme and can reduce the number of the input pins up to 50% by sharing the domain\`s and the range\`s data input pins in the proposed VLSI array architecture. Also, we can reduce the input pins and simplify the internal operation circuit of the processing elements by eliminating a few number of bits of the least significant bits of the input data. We simulated using the 256$\times$256 and 512$\times$512 Lena images to verify performance of the proposed method. As the result of simulation, we can decompress the original image with about 32dB(PSNR) in spite of elimination of the least significant 2-bit in the original input data, and additionally reduce the number of input pins up to 25% compared to VLSI array sharing input pins of range and domain.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.11-19
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• 2004

A software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software, is usually used for LEO satellites. This paper proposes a new power-stage circuit that can be available for modularization of a power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of the proposed power-stage and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stage.