• Title/Summary/Keyword: circuit power

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Experiment on DC Circuit Breaker for Inductive Load by Improved Magnetic Arc-extinguisher and Arc-Attenuation Circuit (개선된 자기소호회로와 아크전압 억제회로를 사용한 유도성 부하의 직류차단 특성 실험)

  • Lee, Sung-Min;Kim, Hyo-Sung
    • The Transactions of the Korean Institute of Power Electronics
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    • v.17 no.6
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    • pp.495-499
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    • 2012
  • Recently, DC distribution systems become hot issues since DC type loads increase rapidly according to the expansion of IT equipment such as computers, servers, and digital devices; DC type loads will cover 50% for all electricity loads in 2020 which was mere 10% in 2000. DC distribution systems are also accelerated by the expansion of renewable power systems since they are easy to be interfaced with DC grids rather than AC grids. However, removing the fault current in DC grids is comparably difficult since the current in DC grids has non zero-crossing point like in AC grids. Thus, developing dedicated DC circuit breakers for DC grids is necessary to get safety for human and electrical facilities. Magnet arc extinguishing method is proper to small size DC circuit breakers. However, simple Magnet arc extinguishing method is not enough to break inductive fault currents. This paper proposed a novel DC circuit breaker against inductive fault current defined by IEEE C37.14-2004 Standard for Low-Voltage DC Power Circuit Breakers Used in Enclosures. The performance of the proposed DC circuit breaker was verified by an experimental circuit breaker test system built in this research.

Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor (슬립 트랜지스터를 이용한 저 전력 MOS 전류모드 논리회로 구조)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.2
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    • pp.69-74
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    • 2008
  • This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

A Novel DC Solid-State Circuit Breaker for DC Grid (DC Grid를 위한 새로운 구조의 DC Solid-State Circuit Breaker)

  • Kim, Jin-Young;Kim, In-Dong;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
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    • v.17 no.4
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    • pp.368-376
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    • 2012
  • According to developed distributed generators, Solid State Circuit Breaker(SSCB) is essential for high power quality of DC Grid. In this paper, a simple and new structure of DC SSCB with a fast circuit breaker and fault current limiter is proposed. It can help to choice low specification of elements because of the limiting of fault current and achieve economic efficiency for minimizing auxiliary SCRs. Also all of SCRs have little switching loss because they operate under ZVS and ZCS. Through simulations and experiments of short-circuit fault, the performance characteristic of proposed circuit is verified and a guideline is so suggested that the DC SSCB is applied for a different DC grid using formulas.

A study on the improvement of impedance decline in PLC (PLC에서의 임피던스 저하 개선에 관한 연구)

  • Choi, Tae-Seop;Ahn, In-Soo
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.42 no.3
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    • pp.7-12
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    • 2005
  • In this paper, we used class D amplification circuit to improve the decline of error rate caused by low impedance in the Power Line Communication. We manufactured voltage drive circuit and current drive circuit that are driven circuit of power line modem on the present and made a comparison experiment with drivel circuit that uses class D amplifier proposed in this paper. As a result of Experiment, We showed that it has great superiority over other existing drive circuits at rapid impedance change in power line channel.

Three-phase Fault Calculation by IEC 60909 (IEC 60909에 의한 삼상 고장계산)

  • Son, Seok-Geum
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.63 no.1
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    • pp.12-18
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    • 2014
  • This paper analyzes how to calculate the three phase short circuit current calculation procedures used in the IEC 60909 short circuit. It presented the new procedure of the fault current for the interrupting capacity of the circuit breaker. This procedure is applied to the future power system and calculates the fault current. Power demands are increased because of the growth of the economy for this reason, the fault current of the power system is largely increased and the fault current procedure for the proper interrupting capacity calculation of the existing or the new circuit breaker is essential. How to calculate the three phase short circuit current for ac electrical system and select the high voltage and low voltage circuit breaker based on IEC 60909 standards.

Analysis and optimization of Wiel-Dobke synthetic testing circuit parameters (Weil-Dobke 합성단락 시험회로의 Parameter 분석과 최적화)

  • Kim, Maeng-Hyun;Rhyou, Hyeong-Kee;Park, Jong-Wha;Koh, Hee-Seog
    • Proceedings of the KIEE Conference
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    • 1995.07b
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    • pp.623-627
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    • 1995
  • This paper describes analysis and optimization of Weil-Dobke synthetic testing circuit parameters, which is efficient and economical test method in high capacity AC circuit breaker. In this paper, analysis of synthetic short-circuit test circuit parameter proposed nondimensional factor that is reciprocal comparison value of circuit parameter and is not related to rated of circuit breaker, in particular, this study induce minimization of required energy of critical TRV generation specified in IEC 56 standards and present optimal design of synthetic short circuit testing facilities.

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A Low-Power Current-Mode CMOS Voltage Reference Circuit (저전력 전류모드 CMOS 기준전압 발생 회로)

  • 권덕기;오원석
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1077-1080
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    • 1998
  • In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a $0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than $7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from $-30^{\circ}C$ to $130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and $T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation.

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A Study on the Verification Scheme for Electrical Circuit Analysis of Fire Hazard Analysis in Nuclear Power Plant (원전 화재위험도분석에서 전기회로분석 검증방안에 관한 연구)

  • Yim, Hyuntae;Oh, Seungjun;Kim, Weekyong
    • Journal of the Korean Society of Safety
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    • v.30 no.3
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    • pp.114-122
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    • 2015
  • In a fire hazard analysis (FHA) for nuclear power plant, various electrical circuit analyses are performed in the parts of fire loading analysis, fire modeling analysis, separation criteria analysis, associated circuit analysis, and multiple spurious operation analysis. Thus, electrical circuit analyses are very important areas so that reliability of the analysis results should be assured. This study is to establish essential electrical elements for each analysis for verification of the reliability of the electrical circuit analyses in the fire hazard analysis for nuclear power plants. Applying the results derived by the study to domestic nuclear power plants, it is expected to determine the adequacy of the fire hazard analysis report and contribute to the reliability of the fire hazard analysis of those plants.

Design and characteristics of operating circuit for the LED Traffic Signal Lamp (LED 교통 신호등의 구동 회로 설계 및 특성)

  • No, Kyung-Ho;Lim, Byoung-No;Park, Jong-Yeun
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2005.05a
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    • pp.106-110
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    • 2005
  • In this paper, LED traffic signal lamp's operating circuit using Flyback converter and PFC IC has been presented. Most power conversion circuits use PFC IC for Power Factor Correction. The design parameter's value of Flyback converter has been proposed and the error amplifier which regulates the output voltage has been designed Besides, the under voltage protection circuit and the over voltage protection circuit for protecting the operating circuit kin unbalance of common electric power source and the temperature compensation circuit for fixed optical output power have been proposed.

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A New Power Factor Correction Circuit Using Boost Converter (부스트 컨버터를 이용한 새로운 역율 개선회로)

  • 김만고
    • Journal of Advanced Marine Engineering and Technology
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    • v.21 no.2
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    • pp.178-185
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    • 1997
  • According to the wide - spread use of rectifier in electronic equipments, such problems as electronic components failures or equipment disorders have been occurred due to current harmonics. To overcome these problems, power factor correction circuits employing boost converter have been used. The high switching stress of boost converter can be reduced by snubber circuit. Recently, research activities in snubber circuits have been directed to energy recovery snubber for improving the efficiency of power converter. In this study, a new passive snubber circuit which can recover trapped snubber energy without added control is proposed for boost converter. The control of boost converter with proposed snubber is the same as the conventional one. In addition, the energy recovery circuit can be implemented with a few passive components. The circuit operation is confirmed through simulation.

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