• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.30-37
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• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.541-544
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• 2004

This paper presents a new circuit panitioning algorithm using wire redundancy removal. This algorithm consist of the two steps. In the first step. We propose a new IIP(Iterative Improvement Partitioning) technique that selects the method to choice cells according to improvement status using two kinds of bucket structures, the one kept by total gain, and the other by updated gain. In the second step, we select the target wire in the cut-set. We add a alternative wire in the circuit to remove the target wire. For this we use wire redundancy removal and addition method The experimental results on MCNC benchmark circuits show improvement up to $41-50\%$ in cut-size over previous algorithms

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.105-113
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• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.46-58
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• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.16-23
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• 1998

In this paper, we present a fast and efficient Iterative Improvement Partitioning(IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. The IIP algorithms are very widely used in VLSI circuit partition due to their time efficiency. As the performance of these algorithms depends on choices of moving cell, various methods have been proposed. Specially, Cluster-Removal algorithm by S. Dutt significantly improved partition quality. We indicate the weakness of previous algorithms wjere they used a uniform method for choice of cells during for choice of cells during the improvement. To solve the problem, we propose a new IIP technique that selects the method for choice of cells according to the improvement status and present hybrid bucket structures for easy implementation. The time complexity of proposed algorithm is the same with FM method and the experimental results on ACM/SIGDA benchmark circuits show improvment up to 33-44%, 45%-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with less CUP tiem, it outperforms Paraboli and MELO represented constructive-partition methods by about 12% and 24%, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.69-77
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• 1998

This paper presents a new efficient and stable multilevel partitioning algorithm for VLSI circuit design. The performance of multilevel partitioning algorithms that are proposed to enhance the performance of previous iterative-improvement partitioning algorithms for large scale circuits, depend on choice of construction methods for partition hierarchy. As the most of previous multilevel partitioning algorithms forces experimental constraints on the process of hierarchy construction, the stability of their performances goes down. The lack of stability causes the large variation of partition results during multiple runs. In this paper, we minimize the use of experimental constraints and propose a new method for constructing partition hierarchy. The proposed method clusters the cells with the connection status of the circuit. After constructing the partition hierarchy, a partition improvement algorithm, HYIP$^{[11]}$ using hybrid bucket structure, unclusters the hierachy to get partition results. The experimental results on ACM/SIGDA benchmark circuits show improvement up to 10-40% in minimum outsize over the previous algorithm $^{[3] [4] [5] [8] [10]}$. Also our technique outperforms ML$^{[10]}$ represented multilevel partition method by about 5% and 20% for minimum and average custsize, respectively. In addition, the results of our algorithm with 10 runs are better than ML algorithm with 100 runs.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.557-560
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• 1988

In this paper, we present a new k-way partitioning algorithm for a graph of an electrical circuit wherein nodes and edges are regarded as cells (modules) and nets, respectively. In contrast to the previous work, our method is based upon a linearly ordered partition paradigm. We also claim that the maximum number of netcuts mostly governs the performance of k-way partitioning, thus having influence on the construction of a new cost function. In addition, our approach elaborates upon balancing the partition size. Our experiments show excellent results in comparison with previous k-way partitioning algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.21-28
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• 1998

In this paper, we propose an efficient linear ordering algorithm, called LIME, for netlist partitioning. LIME incrementally merges two segments which are selected based on the proposed cost function until only one segment remains. The final resultant segment then corresponds to the linear ordering. LIME also runs extremely fast, because it exploits sparsity of netlist. Compared to the earlier work, the proposed algorithm is eight times faster in producing linear ordering and yields an average of 17% improvement for the multi-way scaled cost partitioning.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.4
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• pp.11-19
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• 2013

In this paper we present a reodered simulated-anealing algorithm which is capable of applying odering based k-way partitioned clusters. This method is used for improvement of the objectives of partitioning which are k-way partitioned by using odering algorithm. It changes the positions of the clusters and the vertices in each clusters. Reodered vertices are splitted by using DP-RP method and this process has an opportunity to improve the objective functions. This algorithm has advantages to improve the quality of the solutions for various purposes. Experimental results on several graphs demonstrate that proposed algorithm provides substantial enhancement.