Journal of the Korean Institute of Telematics and Electronics C (전자공학회논문지C)
- Volume 35C Issue 4
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- Pages.30-37
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- 1998
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- 1226-5853(pISSN)
Test Generation for Sequential Circuits Based on Circuit Partitioning
회로 분할에 의한 순차회로의 테스트생성
Abstract
In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.
Keywords