• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2003년도 춘계학술대회
• /
• pp.729-733
• /
• 2003

Hybrid RMU is a kind of power circuit breaker and protects electric devices from over-current. In this paper we built a dynamic model of RMU driving mechanism using ADAMS and performed a optimal design of several design parameters. Finally we developed a prototype of RMU driving mechanism through results of analysis and confirmed it to satisfy design requisitions.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2008년도 제39회 하계학술대회
• /
• pp.854-855
• /
• 2008

This paper deals with the computation error produced in the time step analysis for a electric machine with eddy current. To investigate the error in quantity, the analytic equations representing the steady state results of time-step analysis are deduced. Using the equations, the characteristics of errors are calculated for a general electric circuit, with variation of the circuit parameters and step size.

• 한국세라믹학회지
• /
• 제28권5호
• /
• pp.383-389
• /
• 1991

The analysis of degradation phenomena of poled PZT ceramics was investigated relate to piezoelectric equivalent circuit elements. As a result, in the case of impressed mechanical shock on poled specimen of degradation phenomena was explained by domain rearrangement, and in the case of left in air, degradation phenomena was explained by space charge diffusion.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 하계학술대회 논문집 B
• /
• pp.1022-1024
• /
• 2004

This paper presents a design and characteristics analysis of an SRM drive for EPS application. A rack mounted EPS system is considered in this paper. In the unrestricted design conditions, motor parameters are determined for sufficient torque and speed with some restrictions. For the smooth torque generation and simple circuit of power system, 12/8 motor drive is considered. With FEM and magnetic circuit analysis, redesigned motor is simulated to meet the requirement of specifications. Effectiveness of the suggested SRM drive for EPS application is verified by redesigned motor drive tests.

• International journal of advanced smart convergence
• /
• 제11권4호
• /
• pp.96-103
• /
• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• 한국산업융합학회 논문집
• /
• 제26권5호
• /
• pp.953-965
• /
• 2023

The stratospheric drones are developed to perform missions such as weather observation, communication relay, surveillance, and reconnaissance at 18km to 20km, where climate change is minimal and there is no worry about a collision with aircraft. It uses solar panels for daytime flights and energy stored in batteries for night flights, providing many advantages over existing satellites. The electrical and power systems essential for stratospheric drone flight must ensure reliability, efficiency, and lightness by selecting the optimal circuit topology. Therefore, it is necessary to analyze the circuit topology of various types of multi-level inverters with high redundancy that can ensure the reliability and efficiency of the motor driving power required for stable long-term flight of stratospheric drones. By quantifying the switch element voltage drop and the number and weight of inverter components for each topology, we evaluate efficiency and lightness and propose the most suitable circuit topology for stratospheric drones.

• 전기학회논문지
• /
• 제64권3호
• /
• pp.485-491
• /
• 2015

This paper shows the design improvement and test model of FAU (Frequency Analysis Unit) in PDD (Partial Discharge Diagnosis system) for 800kV GIS (Gas Insulated Switchgear). We found some problems during operation of previous FAU, such as the aging of fiber-optic converter that can cause communication error, the malfunction of signal analysis circuit etc. And then we solved those problems by design improvement and verified the performance through type test. To monitor partial discharge, the performance of UHF sensor is important but the performance of frequency analysis unit is also very important. So we solved communication error, the malfunction of signal analysis circuit and then increased the operation reliability of FAU by improving fiber-optic converter and signal analysis circuit. Accredited testing laboratory carried out the performance verification test according to performance test criteria and procedure of reliability test standards, IEC-60225, 61000 and 60068 etc. We confirmed the test results which correspond with the performance test criteria.

• Journal of Electrical Engineering and Technology
• /
• 제9권6호
• /
• pp.1789-1794
• /
• 2014

This paper suggests an application method for a superconducting fault current limiter (SFCL) using an evaluation index to estimate the risk regarding the short-circuit capacity of the circuit breaker (CB). Recently, power distribution systems have become more complex to ensure that supply continuously keeps pace with the growth of demand. However, the mesh or loop network power systems suffer from a problem in which the fault current exceeds the short-circuit capacity of the CBs when a fault occurs. Most case studies on the application of the SFCL have focused on its development and performance in limiting fault current. In this study, an analysis of the application method of an SFCL considering the risk of the CB's short-circuit capacitor was carried out in situations when a fault occurs in a loop network power system, where each line connected with the fault point carries a different current that is above or below the short-circuit capacitor of the CB. A loop network power system using PSCAD/EMTDC was modeled to investigate the risk ratio of the CB and the effect of the SFCL on the reduction of fault current through various case studies. Through the risk evaluations of the simulation results, the estimation of the risk ratio is adequate to apply the SFCL and demonstrate the fault current limiting effect.

• 한국통신학회논문지
• /
• 제24권9A호
• /
• pp.1434-1441
• /
• 1999

본 논문에서는 Hairpin Line 여파기의 정확한 해석 및 설계를 위한 등가회로를 제시하였으며 제시된 등가회로의 유효성을 컴퓨터 시뮬레이션과 설계를 통해 입증하였다. Hairpin Line 여파기에 대한 설계식은 다양하게 제시되었으나, 인접하지 않는 소자간의 상호 연결성을 포함한 실제적으로 간단화된 등가회로는 아직 명시되고 있지 못하다. 본 논문에서는 회로 duality을 이용하여 Hairpin Line 여파기 회로의 모든 개방단자를 단락단자로 변환하고, 변환된 회로를 그래프 모델로 표시하였다. 또한 각 단자에서의 경계조건으로부터 보다 간략화된 회로모델을 구하고 역 dual구조로 변환하여 Hairpin Line 여파기에 대한 간단화된 등가회로를 유도하였다.

• Transactions on Electrical and Electronic Materials
• /
• 제17권2호
• /
• pp.79-85
• /
• 2016

In this study, we proposed a new single-stage small power MH lamp electronic ballast and power-factor correction circuit with improved circuit by the current of passive power factor correction. Main circuit integrates traditional DC/DC and DC/AC circuits into one-stage DC/AC inverter. Moreover, we described the working principle and control strategy of the new circuit; it's soft switching principle; and resonant element parameter design formula. An experimental prototype of HID lamp electronic ballast with output power of 70 W was built to verify the feasibility of the analysis and design. The simulation and experimental results proved that the power factor of this circuit could reach 94%, with efficiency of 90%. The input current harmonics conform to IEC 61000-3-2 standards and its cost is low. These superior performances of the new circuit indicate certain practical values.