• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• 한국기계가공학회지
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• 제2권2호
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• pp.37-44
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• 2003

Composite materials are widely used to make all kinds of machine parts, internal and structural materials of cars, aerospace industries, building structures, ship materials, sporting goods and others. It is worth the while to use composite materials as various substitutions when compared With others. But the use is limited in the field of the mechanical processing because of its difficulties in cutting. The surface roughness of in and out in the hole processing was discussed after cutting the GFRP with HSS drill in the vertical machining center. And it is observed that as it processed more, the powdered chip may be got more than the fluid type long chip.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2005년도 춘계학술발표대회
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• pp.1679-1682
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• 2005

최근 SoC를 포함하는 대부분의 임베디드시스템에서는 RTOS가 선택이 아닌 필수적인 구성요소가 됨에 따라 SoC 개발의 초기단계에서부터 RTOS를 도입하는 것이 바람직하다. 하지만, 기존의 범용 RTOS가 제공하는 기능은 대부분 응용 소프트웨어의 개발과 수행을 위한 것으로 SoC 개발 및 검증에는 적합하지 않은 문제점을 가지고 있다. 본 연구에서는 SoC 개발을 위해 운영체제가 만족시켜야할 요구사항을 제시하고, 소프트웨어의 재사용성과 SoC의 검증을 함께 지원하는 VPOS(Verification-Purpose OS)를 개발하였다. VPOS는 초경량의 단순한 계층적 구조(layered structure)를 가지는 RTOS로서 소프트웨어 재사용을 위해 POSIX 표준 API, 유닉스 호환 디바이스 드라이버 인터페이스, HAL 등을 제공한다. 또한 SoC 설계의 검증을 위해 RT 수준의 통합시뮬레이션에 적합한 커널 구조 및 최적화된 코드, 하드웨어 테스트를 위한 쉘 명령어, 응용 소프트웨어의 디버깅을 위한 KREM(kernel resource and event monitoring) 등의 특징을 함께 제공한다.

• 한국통신학회논문지
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• 제22권7호
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• pp.1579-1589
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• 1997

This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.

• 한국레이저가공학회:학술대회논문집
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• 한국레이저가공학회 2006년도 추계학술발표대회 논문집
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• pp.53-81
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• 2006

A COG(Chip on Glass) bonding process that is one of display packaging technology and bonds between driver IC chip and a glass panel using ACF(Anisotropic Conductive Film)has been investigated by using diode laser. This method is possible to raise cure temperature of ACF within one second and can reduce the total process time for COG bonding by a conventional method such as a hot plate. Also we can get good pressure mark on the surface of electrodes and higher bonding strength than that by convention method. Results show that laser COG bonding can give low pressure bonding and decrease a warpage of panel. We believe that it can be applied to fine pitch module.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• 대한전자공학회논문지SD
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• 제45권1호
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• pp.20-27
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• 2008

본 논문에서는 비선형 패턴 분류를 위해 FPGA 칩에 신경회로망을 구현하였다. 병렬처리 연산을 위해 순방향 신경회로망이 구현 되었다. 신경망의 학습을 off-line으로 한 다음에 가중치 값들을 저장하여 사용한다. 예로서, AND와 XOR 논리의 패턴 구분이 수행된다. 실험결과를 통해 FPGA에 구현된 신경회로망이 잘 작동하는 것을 검증하였다.

• 대한의용생체공학회:의공학회지
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• 제21권5호
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• pp.513-517
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• 2000

본 논문에서 제안한 텔레메트리 시스템은 생체신호를 증거리로 전송하기 위한 RF 송신기와 전자파 간섭의 영향이 없는 광을 매체로하는 수신기로 구성된 시스템이다. 따라서 텔레메트리 시스템은 RF 송신부, 광 수신부 및 생체신호 처리를 위한 CMOS 원칩으로 구성되어있으며, 65$\times$125$\times$45mm의 크기이다. 제안된 텔레메트리 장점은 전자파에 노출을 최소화하면서 중거리(50m) 텔레메트리가 가능하여, 자유로운 상태에서의 모니터링이 가능하다.

• ETRI Journal
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• 제43권3호
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• pp.471-482
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• 2021

Several code-division multiple access (CDMA)-based interconnect schemes have been recently proposed as alternatives to the conventional time-division multiplexing bus in multicore systems-on-chip. CDMA systems with a dynamic assignment of spreading codewords are particularly attractive because of their potential for higher bandwidth efficiency compared with the systems in which the codewords are statically assigned to processing elements. In this paper, we propose a novel distributed arbitration scheme for dynamic CDMA-bus-based systems, which solves the complexity and scalability issues associated with commonly used centralized arbitration schemes. The proposed arbitration unit is decomposed into multiple simple arbitration elements, which are connected in a ring. The arbitration ring implements a token-passing algorithm, which both resolves destination conflicts and assigns the codewords to processing elements. Simulation results show that the throughput reduction in an optimally configured dynamic CDMA bus due to arbitration-related overheads does not exceed 5%.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 춘계학술발표대회
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• pp.250-253
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• 2011

Chip manufacture nowadays turned their attention from accelerating uniprocessors to integrating multiple cores on a chip. Moreover desktop graphic hardware is now starting to support general purpose computation. Desktop users are able to use multi-core CPU and GPU as a high performance computing resources these days. However exploiting parallel computing resources are still challenging because of lack of higher programming abstraction for parallel programming. The 2-dimensional discrete cosine transform (2D-DCT) algorithms are most computational intensive part of JPEG encoding. There are many fast 2D-DCT algorithms already studied. We implemented several algorithms and estimated its runtime on multi-core CPU and GPU environments. Experiments show that data parallelism can be fully exploited on CPU and GPU architecture. We expect parallelized DCT bring performance benefit towards its applications such as JPEG and MPEG.