• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.417-419
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• 2004

Because of the demands for high performance and high integrated system, the needs for optimal platform becomes more importance. Optimal platform can handle more data effectively with same resources. AMBA(Advanced Microprocessor Bus Architecture)$^{TM}$ defines on-chip communication standard for designing high performance embedded micro-controllers. It is consisted of AHB, ASB and APB. It can support fast implementation and reliability in system that is composed with reusable IPs. DMAC is one of master in system and generate master signals of AHB to communicate data from one slave(peripheral or memory) to another slave. It can reduce burden of CPU and increase system performance. We designed DMAC based on AMBA and it supports 13 Channels. Each channel can be controlled by software program. It decides channel's priority using round-robin method. It can support P2P, P2M, M2P and P2P communication.

• International Journal of Contents
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• v.7 no.1
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.3
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• pp.49-55
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• 2012

Recently, with the rapid development of android-based smartphones, it is becomes a major security issue that the case of Android platform is an open platform. so it is easy to be a target of mobile virus penetration and hacking. Even there are a variety of security mechanisms to prevent the vulnerable points of the Android platform but the reason of most of the security mechanisms were designed at application-level that highly vulnerable to the attacks directly to the operating system or attacks using the disadvantages of an application's. It is necessary that the complementary of the android platform kernel blocks the kernel vulnerability and the application vulnerability. In this paper, we proposed a secure system using linux-based android kernel applied to LIDS(Linux Intrusion Detection and Defense System) and applied a smart phone with s5pc110 chip. As a result, the unauthorized alteration of the application was prevented with a proposed secure system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• Journal of Radiopharmaceuticals and Molecular Probes
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• v.8 no.2
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• pp.95-101
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• 2022

Microfluidic radioimmunoassay (RIA) platform called µ-RIA spends less reagent and shorter reaction time for the analysis compared to the conventional tube-based radioimmunoassay. This study reported the design of µ-RIA chips optimized for the gamma counter which could measure the small samples of radioactive materials automatically. Compared with the previous study, the µ-RIA chips developed in this study were designed to be compatible with conventional RIA test tubes. And, the automatic gamma counter could detect radioactivity from the ¹²⁵I labeled anti-PSA attached to the chips. Effects of the multi-layer microchannels and two-phase flow in the µ-RIA chips were investigated in this study. The measured radioactivity from the ¹²⁵I labeled anti-PSA was linearly proportional to the number of stacked chips, representing that the radioactivity in µ-RIA platform could be amplified by designing the chips with multi-layers. In addition, we designed µ-RIA chip to generate liquid-gas plug flow inside the microfluidic channel. The plug flow can promote binding of the biomolecules onto the microfluidic channel surface with recirculation in the liquid phase. The ratio of liquid slug and air slug length was 1 : 1 when the ¹²⁵I labeled anti-PSA and the air were injected at 1 and 35 µL/min, respectively, exhibiting 1.6 times higher biomolecule attachment compared to the microfluidic chip without the air injection. This experimental result indicated that the biomolecular reaction was improved by generating liquid-gas slugs inside the microfluidic channel. In this study, we presented a novel µ-RIA chips that is compatible with the conventional gamma counter with automated sampler. Therefore, high-throughput radioimmunoassay can be carried out by the automatic measurement of radioactivity with reduced radiowaste generation. We expect the µ-RIA platform can successfully replace conventional tube-based radioimmunoassay in the future.

• Smart Structures and Systems
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• v.12 no.1
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• pp.23-39
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• 2013

In this article, a smart multifunctional optical system-on-a-chip (SOC) sensor platform is presented and its application for fiber Bragg grating (FBG) sensor interrogation in optical sensor networks is investigated. The smart SOC sensor platform consists of a superluminescent diode as a broadband source, a tunable microelectromechanical system (MEMS) based Fabry-P$\acute{e}$rot filter, photodetectors, and an integrated microcontroller for data acquisition, processing, and communication. Integrated with a wireless sensor network (WSN) module in a compact package, a smart optical sensor node is developed. The smart multifunctional sensor platform has the capability of interrogating different types of optical fiber sensors, including Fabry-P$\acute{e}$rot sensors and Bragg grating sensors. As a case study, the smart optical sensor platform is demonstrated to interrogate multiplexed FBG strain sensors. A time domain signal processing method is used to obtain the Bragg wavelength shift of two FBG strain sensors through sweeping the MEMS tunable Fabry-P$\acute{e}$rot filter. A tuning range of 46 nm and a tuning speed of 10 Hz are achieved. The smart optical sensor platform will open doors to many applications that require high performance optical WSNs.

• Journal of Korea Multimedia Society
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• v.18 no.2
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• pp.244-252
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• 2015

This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using a FPGA-based prototyping platform environment for design and verification of the target SoC. To ensure that the implemented face recognition SoC satisfies the required performances metrics, time analysis and recognition tests were performed. The motivation behind the work is a single chip implementation of face recognition system for target applications.

• Electronics and Telecommunications Trends
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• v.38 no.1
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• pp.9-16
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• 2023

In the rapidly growing field of quantum computing, it is evident that a robust supply chain is needed for commercialization or large-scale production of quantum chips. As a result, the success of many R&D projects worldwide relies on the development of quantum chip foundries. In this paper, a variety of quantum chip foundries, particularly the ones creating photonic integrated circuit (PIC) quantum chips, are reviewed and summarized to demonstrate current technological trends. Global projects aiming to establish new foundries, as well as information regarding their respective funding, are also included to identify the evolutionary direction of quantum computing infrastructure. Furthermore, the potential application of lithium niobate as a novel material platform for quantum chips is also discussed.

• 한국생물공학회:학술대회논문집
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• 2003.10a
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• pp.682-682
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• 2003

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.