• 한국세라믹학회지
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• 제49권6호
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• 한국전기전자재료학회논문지
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• 제33권6호
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제36회 동계학술대회 초록집
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• pp.132.1-132.1
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제36회 동계학술대회 초록집
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• pp.105.1-105.1
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제36회 동계학술대회 초록집
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• pp.99.1-99.1
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• 2009

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.789-790
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• 2013

기존 MOS (Metal-Oxide-Semiconductor) 소자의 게이트 산화막으로 사용된 $Er_2O_3/SiO_2$ 더블레이어 층은 낮은 누설전류와 높은 캐패시턴스를 갖는 장점을 가지고 있다. 본 논문에서는 이 더블레이어 층을 비휘발성 메모리 소자의 전하포획층으로 처음 적용하여 우수한 성능의 메모리 특성을 얻을 수 있었다. 소자를 제작하기 전에 EDISON Nanophysics 시뮬레이션을 통해 낮은 누설 전류값과 높은 캐패시턴스 값을 기준으로 하여 산화막 두께를 최적화하였다. 이 후, 최적화된 조건으로 금속실리사이드 소스/드레인, 10 um/ 10um의 채널 넓이/길이를 갖는 비휘발성 메모리 소자를 제작하였다. 그 결과, 11 V, 50 ms의 프로그램 특성, -11 V, 500 ms의 소거 특성 및 10년의 기억유지 특성, $10^4$의 내구성 특성을 얻을 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.53-53
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• 2009

Charge trap flash memory devices with modified tunneling barriers were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were used as engineered tunneling barriers. The VARIOT type tunneling barrier composed of oxide-nitride-oxide (ONO) layers revealed reliable electrical characteristics; long retention time and superior endurance. On the other hand, the CRESTED tunneling barrier composed of nitride-oxide-nitride (NON) layers showed degraded retention and endurance characteristics. It is found that the degradation of NON barrier is associated with the increase of interface state density at tunneling barrier/silicon channel by programming and erasing (P/E) stress.