• Journal of information and communication convergence engineering
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• 제15권1호
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• pp.62-71
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• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• 대한전자공학회논문지SD
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• 제40권7호
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• pp.532-541
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• 2003

메모리에서의 대부분의 전력은 프리디코더 라인, 워드 라인, 그리고 비트 라인 등과 같은 커패시턴스가 큰 라인들에서 소모된다. 이 라인들에서의 전력 소모를 줄이기 위하여 전하 재활용과 전하 공유를 사용한 세 가지 기법들이 제안되었다. 이 기법들은 전하 재활용 프리디코더(charge recycling predecoder, CRPD), 전하 재활용 워드 라인 디코더(charge recycling word line decoder, CRWD), 그리고 롬을 위한 전하 공유 비트 라인(charge sharing bit line, CSBL)이다. CRPD와 CRWD는 프리디코더 라인과 워드 라인의 전하를 재활용하여 소모 전력을 반으로 줄여주고, 전하 공유 기법을 사용하는 CSBL은 롬 비트라인의 스윙 전압을 낮춤으로써 소모 전력을 크게 줄여준다. CRPD, CRWD, 그리고 CSBL의 소모 전력은 기존의 82%, 72%, 그리고 64%이다. 제안된 세 가지 기법들을 사용하는 전하 재활용 전하 공유 롬(charge recycling and charge sharing ROM, CRCS-ROM)이 0.35㎛ CMOS공정으로 제작되었다. 제작된 8K×16비트 CRCS-ROM의 코어 크기는 0.51㎟이고 3.3V 전원과 100㎒ 동작 주파수에서 8.63㎽ 을 소모하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.97-99
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• 2008

It is possible to suppress voltage drops, power loading fluctuations and regeneration power lapses for DC railway systems by applying an energy storage system. Recently the electric double layer capacitor (EDLC) of the rapid charge/discharge type has been developed and used in wide ranges. The on board energy storage system with supercapacitor for railway vehicles presented in this paper seems to be a reliable technical solution with an enormous energy saving potential. In this paper, an efficient charge and discharge control method of a bidirectional DC-DC converter using the supercapacitor is proposed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• 대한전자공학회논문지SD
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• 제41권3호
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• pp.101-108
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• 2004

단열회로를 이용하여 16-bit ALU와 단열회로에 4가지 위상을 가지는 전원클럭을 공급하기 위한 전원클럭 발생기를 설계하였다. 4개의 전원클럭 신호선의 전하는 AC 형태의 전원클럭을 통해서 복원되어 에너지 소모를 줄인다. 구현에 사용한 단열회로는 ECRL(efficient charge recovery logic) 형태를 기본으로 하였으며 0.35㎛ CMOS 공정을 사용하여 설계하였고 3.3V 전원을 사용하였다. 회로설계 후 layout을 진행하였으며, layout 후 LPE(layout parasitic extraction)를 수행하여 이를 모의실험에 사용하였다. 모의실험결과 전원클럭 발생기를 포함한 단열회로를 이용한 ALU는 동일한 구조를 갖는 기존의 CMOS ALU보다 1.15～1.77배 정도의 에너지소모를 감소 시켰다.

• 한국염색가공학회지
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• 제35권1호
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• pp.20-28
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• 2023

In this study, TPU resin for coating was prepared by varying the mixing ratio of antistatic TPU and recycled TPU to manufacture permanent antistatic materials. The coated yarn was prepared by coating on the nylon yarn, and then the thermal, rheological, mechanical properties and antistatic properties were analyzed. In addition, antistatic properties and durability were confirmed after manufacturing UD fabrics using coated yarns. The mixing ratio of antistatic TPU and recycled TPU was most appropriate at 4:6, and the antistatic property had a surface resistance of 2.20 × 10⁹ Ω and a static charge of 398 V. In the coating process, the coating speed was most appropriate at 0.21 m/s, and the surface resistance of the UD fabric manufactured with the coated yarn manufactured under this condition was 6.80 × 10⁹ Ω and the static charge was 484 V. The UD fabric had a surface resistance of 7.21 × 10⁹ Ω and a static charge of 517 V after washing 10 times, and it was confirmed that the permanent antistatic property was excellent.

• 환경위생공학
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• 제14권2호
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• pp.96-104
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• 1999

A questionary survey was conducted to investigate citizen's attitude to the treatment of food wastes in Miryang city. In this study, collection effectives was 87.8%, as 281 individuals among 320 individuals. After volume-base charge system, 86.8% of answers perform source separation and 60.9% of respondents separate everything of recycle goods. The majority of respondents discharge food waste using standard envelope. The biggest problems for deposition of the food wastes are offensive odor and worm for reasons of sanitation. Almost citizens think that the period of deposition suit from two days to three days. More than 90.0% of the citizens recognized that compost products made from food wastes and recognition of the people for the composting and composting facilities was affirmative. Majority of the respondents thought that the administration and the provincial government need activity publicity for the source separation fixations of the food wastes.

• 한국시스템다이내믹스연구
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• 제9권2호
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• pp.129-154
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• 2008

As a practical means to upgrade urban sustainability, this paper focuses on resource cyclical systems concerned with the waste of electric and electronic equipment (WEEE) in Korea. Borrowing System Dynamics concepts and approaches, it examines behavioral changes of WEEE dynamics to observe whether the existing management methods can be readjusted. The measurement is based upon both reuse and material and thermal recycle simulation works in the individual stage of WEEE discharge, collection, and treatment, going beyond the traditional recycle-only customs. This research estimates that the newly introduced Extended Producer Responsibility (EPR) system would definitely exert a significant impact on the final stage of WEEE treatment, decreasing the final treatment volume in the first half of the research period. The trend, nonetheless, would be reversed in the second half, mainly owing to the additional waste volume originated from the local government and recycling center. Sensitivity analysis poses, among others, that the local government-supported reuse center should take charge of a pivotal role in the long run. The research also shows that sufficientand necessary conditions for the WEEE management and treatment should be given to the combined efforts, both from the private sectors and the public domains. Based on these research findings, the paper recommends that key stakeholders including the producer and the public organizations should devise how to jointly carry out specific agenda centered around partnership or network buildings.

• 대한전자공학회논문지SD
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• 제46권5호
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• pp.25-31
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• 2009

본 논문에서는 공급전압의 전하를 재활용하여 전력소모를 줄인 저전력 SRAM(Low power SRAM using supply voltage charge recycling: SVCR-SRAM)을 제안하였다. 제안한 SVCR-SRAM은 SRAM 셀 블록을 두 개의 셀 블록으로 나누어 두 종류의 공급전압을 공급한다. 이중 하나는 $V_{DD}$와 $V_{DD}/2$이고, 다른 하나는 $V_{DD}/2$와 GND이다. N비트 셀들이 연결되었을 때 $V_{DD}$와 $V_{DD}/2$의 전원으로 동작하는 N/2비트의 셀들에서 사용된 전하는 나머지 $V_{DD}/2$와 GND의 전원으로 동작하는 N/2비트의 셀들에서 재활용된다. SVCR 기법은 전력소모가 많은 비트라인, 데이터 버스, SRAM 셀에서 사용되어 전력소모를 줄여준다. 다른 부분들에서는 동작속도를 높이기 위해 $V_{DD}$와 GND의 공급전압을 사용하였다. 또한, SVCR-SRAM에서는 Body-effect로 인한 SRAM 셀들의 누설전류가 크게 감소하는 효과가 있다. 검증을 위하여, 64K비트($8K{\times}8$비트)SRAM chip을 $V_{DD}=1.8V,\;0.18{\mu}m$ CMOS 공정으로 구현하였다. 제작된 SVCR-SRAM에서는 쓰기전력의 57.4%와 읽기전력의 27.6%가 줄었다.