• 전기학회논문지
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• 제60권2호
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• 전력전자학회논문지
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• 제12권5호
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• pp.386-393
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• 2007

본 논문에서는 CIM(Current Injection Method)을 이용한 charge-pump방식의 plasma backlight용 고압 inverter회로를 제안한다. 고압 inverter에서 에너지 회수회로의 채용은 새로운 시도로서 에너지회수 이외에도 noise에 의한 시스템의 불안정성과 방전안정화에 기여하고 있다. charge-pump방식으로 스위치류의 내압을 저감하므로 cost면에서 매우 유리한 조건을 확립하였으며 CIM(Current Injection Method)방식의 적용으로 high speed 에너지 회수를 가능하게 하였다. 그리고 제안회로의 동작을 모드별로 해석하였으며, 실제 32" 패널에 적용하여 실험함으로써 제안한 회로의 유용성을 입증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.469-471
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• 2008

전하 펌프는 위상 고정 루프의 성능에 영향을 준다. 전하 펌프 설계에 있어서 전류 부정합, 전하 공유, 전하 주입, 누설 전류 등을 고려할 필요가 있다. 본 논문에서는 기존의 고속 전하 펌프의 전류 정합성을 개선한 새로운 전하 펌프 회로를 제안하였다. 전류 부정합을 줄이기 위해 주로 사용되는 간단한 방법으로는 캐스코드를 이용하여 전하 펌프의 출력 저항을 증가시키는 방법이 있다. 그러나 캐스코드 방법을 사용하면 전하펌프의 출력 범위에 제약을 받게 되므로 전원 전압이 낮아짐에 따라 적용하기가 힘들어진다는 단점이 있다. 따라서 본 논문에서는 캐스코드를 적용하지 않고 연산증폭기를 사용하여 전하펌프의 출력 범위 전체에서 우수한 전류 정합 특성을 갖는 회로를 제안하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.331-338
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• 2014

A charge-pump circuit using a current-bypass technique, which suppresses charge sharing and reduces the sub-threshold currents, helps to decrease phase-locked loop (PLL) jitter without resorting to a feedback amplifier. The PLL shows no stability issues and no power-up problems, which may occur when a feedback amplifier is used. The PLL is implemented in 0.11-${\mu}m$ CMOS technology to achieve 0.856-ps RMS and 8.75-ps peak-to-peak jitter, which is almost independent of ambient temperature while consuming 4 mW from a 1.2-V supply.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.381-383
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• 2007

Charge-pump high voltage inverter for Plasma backlight with CIM(Current Injection Method) is proposed in this paper. Adoption of ERC is a new attempt in high voltage inverter so that it is not only energy recovery but also improvement of discharge stability and system unstability which is interrupted by noise. Using a charge-pump technique enables low voltage switches to be usable, the cost can be reduce. CIM is adopted to achieve high speed energy recovery in proposed circuit. Operations of the proposed circuit are analyzed for each mode. The proposed circuit is verified to be applicable on a 32 inch plasma backlight panel by experimental results.

• International Journal of Air-Conditioning and Refrigeration
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• 제16권3호
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• pp.77-82
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• 2008

For heat pumps used in a cold region, it is very important to obtain appropriate heating capacity. Several studies using a variable speed compressor and an additional heater have been performed to enhance heating capacity at low ambient temperatures. However, for outdoor temperature conditions below $-15^{\circ}C$, it is still difficult to obtain enough heating capacity above the rated value. In recent studies, the application of gas injection technique into a two-stage heat pump yielded noticeable heating performance improvement at low temperature conditions. In this study, the heating performance of a two-stage gas injection heat pump with a rated capacity of 3.5 kW was measured and analyzed by varying refrigerant charge amount and EEV opening at the standard heating condition. The heating performance of the two-stage gas injection heat pump was compared with that of a two-stage non-injection heat pump. The heating capacity and COP of the two-stage gas injection heat pump were improved by 2-10% at the optimal charging condition over those of the two-stage non-injection heat pump.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• 설비공학논문집
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• 제21권8호
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• pp.425-432
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• 2009

In this study, the improvement of cooling capacity by applying gas injection technique in a two-stage heat pump using R410A was experimentally investigated. A twin rotary type compressor with gas injection was applied to the heat pump system. The optimum refrigerant charge for the injection and the non-injection cycles was selected to achieve the maximum COP at the cooling standard condition. The injection cycle showed less optimum refrigerant charge than that of the non-injection cycle. The cooling performances of the injection and the non-injection cycles were measured and compared by varying compressor frequency from 40 to 90 Hz. The cooling capacity of the gas injection cycle was 1.6% -11.3% higher than that of the non-injection cycle. The COP of the gas injection cycle was 13.7% to 28.9% higher than that of the non-injection cycle at the same cooling capacity. The heat pump system showed stable operation after 30% of the injection valve opening.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.446-448
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• 2008

A new plasma display panel sustaining driver using single side sustaining technique with the dual resonant method is proposed. Since this circuit enables to reduce switches in energy recovery circuit with keeping voltage stress like that of prior circuit, it can be low cost circuit comparing with a conventional driver. To integrate sustain function into one side with single power source in the driver, a charge pump method is adopted to make negative sustaining voltage and achieve dual resonant energy recovery on sustaining modes.