• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Journal of the Korean Society of Hazard Mitigation
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• v.10 no.5
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• pp.117-124
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• 2010

Most of the rivers which exist in nature are not a single river but the network that is composed of several branches and mainstreams. The river network are more complicated than other sigle rivers and streams. Therefore the hydraulic characteristics are sensitively changed by reduction and expansion of the width in the confluence or the variation of the flux. In this paper, the hydraulic characteristics were calculated by the change of the width and length in the confluence and the hydraulic model test. The deposit of confluence emerged at the left bank, right bank and the stagnation sector. As the total flow in the branch have increased, stagnation of the left bank and right bank have decreased. When the width of the downstream have been get smaller from 3 m to 2 m, the deposit of the left bank and right bank and stagnation sector have decreased. But as the eddy flow in the center of the confluence is occurred, the erosion has been increased. The result of this paper can be used as a basic data of water management around the junction and for maintenance on the ground of development of the river.

• Journal of Magnetics
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• v.17 no.4
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• pp.302-307
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• 2012

We have designed, fabricated and tested an integrated microfluidic chip with a Planar Hall Effect (PHE) sensor. The sensor was constructed by sequentially sputtering Ta/NiFe/Cu/NiFe/IrMn/Ta onto glass. The microfluidic channel was fabricated with poly(dimethylsiloxane) (PDMS) using soft lithography. Magnetic nanoparticles suspended in hexadecane were used as ferrofluid, of which the saturation magnetisation was 3.4 emu/cc. Droplets of ferrofluid were generated in a T-junction of a microfluidic channel after hydrophilic modification of the PDMS. The size and interval of the droplets were regulated by pressure on the ferrofluid channel inlet. The PHE sensor detected the flowing droplets of ferrofluid, as expected from simulation results. The shape of the signal was dependent on both the distance of the magnetic droplet from the sensor and the droplet length. The sensor was able to detect a magnetic moment of $2{\times}10^{-10}$ emu at a distance of 10 ${\mu}m$. This study provides an enhanced understanding of the magnetic parameters of ferrofluid in a microfluidic channel using a PHE sensor and will be used for a sample inlet module inside of integrated magnetic lab-on-a-chip systems for the analysis of biomolecules.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Applied Science and Convergence Technology
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• v.26 no.3
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• pp.47-49
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• 2017

Photocurrent enhancement has been investigated in monolayer (1L) $MoS_2$ with PbS quantum dots (QDs). A metal-semiconductor-metal (Au-1L $MoS_2$-Au) junction device is fabricated using a standard photolithography method. Considerably improved photo-electrical properties are obtained by coating PbS QDs on the Au-1L $MoS_2$-Au device. Time dependent photoconductivity and current-voltage characteristics are investigated. For the QDs-coated $MoS_2$ device, it is observed that the photocurrent is considerably enhanced and the decay life time becomes longer. We propose that carriers in QDs are excited and transferred to the $MoS_2$ channel under light illumination, improving the photocurrent of the 1L $MoS_2$ channel. Our experimental findings suggest that two-dimensional layered semiconductor materials combined with QDs could be used as building blocks for highly-sensitive optoelectronic detectors including radiation sensors.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.72-78
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• 1990

In this paper, the physical meanings of LDD optimization are treated by numerical simulation and related experiments are attempted to analyzed the optimized LDD structure. Firstly, according to the numerical analysis, the electric field under the n-region near drain is low and uniformly distributed and the current flow is widely distributed in this region under the optimized conditions. It is also found that this optimized point should be achieved by globally optimizing all the process and electrical conditions. Secondly, the maximum electric field, which is obtained from the substrate current to the drain current ratio, is minimized under the optimized condition according to the experiment. Further, the device lifetime is maximized and the n-resistance is changed smoothly from the channel resistance to the $n^+$junction resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.25 no.6
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• pp.324-330
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• 2013

The main objective of this work is to experimentally investigate the effect of inlet geometries on the distribution of two-phase annular flow at header-channel junctions simulating the corresponding parts of compact heat exchangers. The cross-section of the header and the channels were fixed to $16mm{\times}16mm$ and $12mm{\times}1.8mm$, respectively. Experiments were performed for the mass flux and the mass quality ranges of $30{\sim}140kg/m^2s$ and 0.3~0.7, respectively. Air and water were used as the test fluids. Three different inlet geometries of the header were tested:no restriction (case A), a single 8 mm hole at the center (case B), and nine 2 mm holes around the center (case C) at the inlet, respectively. The tendencies of the two-phase flow distribution were different, in each case. For cases B and C (flow resistance exists), more uniform flow distribution results were seen, compared with case A(no flow resistance), due to the flow pattern change to mist flow from annular flow at the inlet, and the flow recirculation near the end plate of the header.

• Journal of Korea Water Resources Association
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• v.51 no.12
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• pp.1273-1284
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• 2018

The flow and bed change were analyzed using the CCHE2D model, which is a two-dimensional numerical model, at a confluence of the Namhan River and Seom River where deposition occurs predominantly after the "Four Major Rivers Restoration Project." The characteristic of the junction is that the tributary of Seom River joined into the curved channel of the main reach of the Namhan River. The CCHE2D model analyzes the non-equilibrium sediment transport, and the adaptation lengths for the bed load and suspended load are important variables in the model. At the target area, the adaptation length for the bed load showed the greatest influence on the river bed change. Numerical simulation results demonstrated that the discharge ratio ($Q_r$) change affected the flow and bed change in the Namhan River and Seom river junction. When $Q_r{\leq}2.5$, the flow velocity of the main reach increased before confluence, thereby reducing the flow separation zone and decreasing the deposition inside the junction. When $Q_r$>2.5, there was a high possibility that deposition would be increased, thereby forming sand bar. Numerical simulation showed that a fixed sand bar has been formed at the junction due to the change of discharge ratio, which occurred in 2013.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.