• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.86.1-86.1
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• 2015

As the feature size of Si-based semiconductor shrinks to nanometer scale, we are facing to the problems such as short channel effect and leakage current. One of the solutions to cope with those issues is to bring III-V compound semiconductors to the semiconductor structures, because III-V compound semiconductors have much higher carrier mobility than Si. However, introduction of III-V semiconductors to the current Si-based manufacturing process requires great challenge in the development of process integration, since they exhibit totally different physical and chemical properties from Si. For example, epitaxial growth, surface preparation and wet etching of III-V semiconductors have to be optimized for production. In addition, oxidation mechanisms of III-V semiconductors should be elucidated and re-growth of native oxide should be controlled. In this study, surface preparation methods of various III-V compound semiconductors such as GaAs, InAs, and GaSb are introduced in terms of i) how their surfaces are modified after different chemical treatments, ii) how they will be re-oxidized after chemical treatments, and iii) is there any effect of surface orientation on the surface preparation and re-growth of oxide. Surface termination and behaviors on those semiconductors were observed by MIR-FTIR, XPS, ellipsometer, and contact angle measurements. In addition, photoresist stripping process on III-V semiconductor is also studied, because there is a chance that a conventional photoresist stripping process can attack III-V semiconductor surfaces. Based on the Hansen theory various organic solvents such as 1-methyl-2-pyrrolydone, dimethyl sulfoxide, benzyl alcohol, and propylene carbonate, were selected to remove photoresists with and without ion implantation. Although SPM and DIO3 caused etching and/or surface roughening of III-V semiconductor surface, organic solvents could remove I-line photoresist without attack of III-V semiconductor surface. The behavior of photoresist removal depends on the solvent temperature and ion implantation dose.

• Membrane Journal
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• v.12 no.4
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• pp.226-239
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• 2002

A process simulation model of pervaporation process has been developed as a design tool to analyse and optimize the dehyhration of organic solvents through a commercial scale of pervaporative plate-and-frame modules that contain a stack of membrane sheets. In the simulation model, the mass balance, the heat balance and the concentration balance are integrated in a finite elements-in-succession method to simulate the overall process. In the integration method, a feed channel between membrane sheets in the modules was taken as differential unit element volume to simplify calculation procedure and shorten computing time. Some of permeation parameters used in the simulation model, were quantified directly from the dehydration experiment of ethanol through $AzeoSep^{TM}$-2002 membrane which is a commercial pervaporation membrane. The simulation model was verified by comparing the simulated values with experimental data. Using the model, continuous and batch pervaporation processes were simulated, respectively, to acquire basic data for analysing and optimizing in the dehydration of ethanol through the membrane. Based on the simulation results, a comparison between the continuous and the batch pervaporation processes would be discussed.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.2
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• pp.171-178
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• 2008

Galileo is the Europe's global navigation satellite system corresponding to the GPS. The GIOVE-A test experiment has been finished and the second test satellite GIOVE-B will be launched soon. The integration of GPS and Galileo lead an increase of visible satellite number. We can obtain an improved navigation performance in signal blocked area such as urban or forest. GPS and Galileo have each time-coordinate system and use the different error model to calculate the navigation solution. In this paper, we studied on GPS and Galileo channel error model and time-coordinate system. Using this result, we implement the integrated navigation algorithm. In simulation, we analyzed the navigation error caused by time and coordinate disagreement and verified performance of integrated navigation algorithm in terms of visible satellite number, DOP(Dilution of Pression) and position error.

• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.102-108
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• 2015

With the constantly increasing demand of domestic and oversea satellite images, there is also a growing demand to rapidly acquire images after the satellite image collection planning of KOMPSAT-2/3/5. Therefore, it has been increasing to use the korea ground station and oversea ground station to keep pace with increased demand. The KARI is operating Data Ingestion System of the KOMPSAT-2/3 in Svalbard, where the satellite images have been received at least four or six times a day. The KARI is planning to operate oversea receiving system for KOMPSAT-5/3A. This paper introduces the polar data ingestion system operating in Norway, and presents the process of design and development for Polar Integration receiving system in preparation of multiple satellite operation.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.313-318
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• 2002

The Integration of agent technology and security technology is needed to many application areas like electronic commerce. This paper suggests a model of extended multi-agent engine which supports privacy, integrity, authentication and non-repudiation on agent communication. Each agent which is developed with the agent engine is composed of agent engine layer and agent application layer. We describe and use the concepts self-to-self messages, secure communication channel, and distinction of KQML messages in agent application layer and messages in agent engine layer. The suggested agent engine provides an agent communication language which is extended to enable secure communication between agents without any modifications or restrictions to content layer and message layer of KQML. Also, in the model of our multi-agent engine, secure communication is expressed and processed transparently on the agent communication language.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.6
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• pp.2720-2728
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• 2012

Recently flexible mobile terminals which can freely change the shape of their device are coming out with the development of the flexible display, high capacity memory and system integration technology. The display and the antenna configuration of the future terminals will be altered according to the QoS (quality of service) and the communication environment of users. In particular, we present the new emergence of a multimedia language for human and system to communicate over subjective concepts, intention of users. The intension of users is expressed by changing the shape of their mobile terminal. In addition, antenna configuration is also related to shape of terminal and QoS of users. Therefore, we set up a specific usage scenarios for future mobile terminals and propose an adaptive MIMO (multiple-input multiple-output) schemes that can maximize channel capacity and fit to QoS of users simultaneously.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of Information Display
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• v.10 no.1
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• pp.33-36
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• 2009

A new hybrid silicon thin-film transistor (TFT) fabrication process using the DPSS laser crystallization technique was developed in this study to realize low-temperature poly-Si (LTPS) and a-Si:H TFTs on the same substrate as a backplane of the active-matrix liquid crystal flat-panel display (AMLCD). LTPS TFTs were integrated into the peripheral area of the activematrix LCD panel for the gate driver circuit, and a-Si:H TFTs were used as a switching device of the pixel electrode in the active area. The technology was developed based on the current a-Si:H TFT fabrication process in the bottom-gate, back-channel etch-type configuration. The ion-doping and activation processes, which are required in the conventional LTPS technology, were thus not introduced, and the field effect mobility values of $4\sim5cm^2/V{\cdot}s$ and $0.5cm^2/V{\cdot}s$ for the LTPS and a-Si:H TFTs, respectively, were obtained. The application of this technology was demonstrated on the 14.1" WXGA+(1440$\times$900) AMLCD panel, and a smaller area, lower power consumption, higher reliability, and lower photosensitivity were realized in the gate driver circuit that was fabricated in this process compared with the a-Si:H TFT gate driver integration circuit

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.