• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.361-364
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• 2002

Shortest path problem belongs to the combinatorial optimization problem and plays an important role in the field of computer aided design. It can either be directly applied as in the case of routing or serves as a important subroutine in more complex problems. In this paper, a systolic array for the SSSP(single-source shortest path problem) was derived. The array was modeled and simulated in RTL level using VHDL, then synthesized to a schematic and finally implemented to a layout using the cell library based on 0.35 $\mu\textrm{m}$ CMOS 1-poly 4-metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.177-180
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• 2000

This paper proposes the optimized hardware architecture for a high performance image downscaler The proposed downscaler uses non-linear digital filters for horizontal and vertical scalings. In order to achieve the optimization, the filters are implemented with multiplexer-adder type scheme and all the filter coefficients are selected on the order of two's power. The performance of the scaler is also verified by comparing with a pixel drop downscaler. The proposed scaler is designed by using the VHDL and implemented by using the IDEC-C632 0.65$\mu\textrm{m}$ cell library.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.238-241
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• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.187-191
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• 2009

This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD ($1,920{\times}1,088$) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.162-167
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• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

• Proceedings of the Korean Society of Sericultural Science Conference
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• 2003.10a
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• pp.143-143
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• 2003

Among all animal species, a few have the remarkable capacity to regenerate a missing part of their body after amputation. The early process of epimorphic regeneration in which dedifferentiation and cell proliferation are involved, provides a useful model to investigate the mechanism of normal development as well as differentiation. To better understand early stage of head regeneration, we have generated 5'-end sequence of 1,592 expressed sequence tags (ESTs) from cDNA library of regenerating tissue. (omitted)

• Proceedings of the Korean Society of Sericultural Science Conference
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• 2003.10a
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• pp.141-142
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• 2003

Partial cDNA sequencing to generate expressed sequence tags (ESTs) is being used at present for the fast and efficient obtainment of a detailed profile of genes expressed in various tissues, cell types, or developmental stages. We describe here the construction, DNA sequencing and sequence profiles of cDNA library from Uroctea lesserti. (omitted)

• Proceedings of the Korean Society of Applied Entomolohy Conference
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• 2001.11a
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• pp.131-131
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• 2001

• Journal of computational fluids engineering
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• v.4 no.3
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• pp.52-62
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• 1999

The development of a parallelized aerodynamic simulation process involving moving bodies is presented. The implementation of this process is demonstrated using a fully systemized Chimera methodology for steady and unsteady problems. This methodology consists of a Chimera hole-cutting, a new cut-paste algorithm for optimal mesh interface generation and a two-step search method for donor cell identification. It is fully automated and requires minimal user input. All procedures of the Chimera technique are parallelized on the Cray T3E using the MPI library. Two and three-dimensional examples are chosen to demonstrate the effectiveness and parallel performance of this procedure.