• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.

• Journal of Microbiology and Biotechnology
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• v.27 no.3
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• pp.507-513
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• 2017

Bacillus subtilis spores can be used for protein display to engineer protein properties. This method overcomes viability and protein-folding concerns associated with traditional protein display methods. Spores remain viable under extreme conditions and the genotype/phenotype connection remains intact. In addition, the natural sporulation process eliminates protein-folding concerns that are coupled to the target protein traveling through cell membranes. Furthermore, ATP-dependent chaperones are present to assist in protein folding. CotA was optimized as a whole-cell biocatalyst immobilized in an inert matrix of the spore. In general, proteins that are immobilized have advantages in biocatalysis. For example, the protein can be easily removed from the reaction and it is more stable. The aim is to improve the pH stability using spore display. The maximum activity of CotA is between pH 4 and 5 for the substrate ABTS (ABTS = diammonium 2,2'-azino-bis(3-ethylbenzothiazoline-6-sulfonate). However, the activity dramatically decreases at pH 4. The activity is not significantly altered at pH 5. A library of approximately 3,000 clones was screened. A E498G variant was identified to have a half-life of inactivation ($t_{1/2}$) at pH 4 that was 24.8 times greater compared with wt-CotA. In a previous investigation, a CotA library was screened for organic solvent resistance and a T480A mutant was found. Consequently, T480A/E498G-CotA was constructed and the $t_{1/2}$ was 62.1 times greater than wt-CotA. Finally, E498G-CotA and T480A/E498G-CotA yielded 3.7- and 5.3-fold more product than did wt-CotA after recycling the biocatalyst seven times over 42 h.

• Korean Journal of Microbiology
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• v.31 no.3
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• pp.197-202
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• 1993

The budding yeast S. cerevisiae contains 10-nm filament ring that lies just inside the plasma memhrane in the region of the mother-bud neck. It is possihle that CDC3. CDCIO, CDCII. CDCI2 genes encode the filaments. Recently it has been shown that the CDC3 and CDCI2 gene products arc localized to [he vicinity of the neck lilaments by immunolluorescence. However. the role of the lilament ring is not clear. In order to find out the role of filament ring. I have tried to clone the similar gene in S. pomhe to the CDC3 in S. cerevisiae. Genomic library was constructed by use of $\lambda$gtll expression vector and screened with CDC3 antibodies. From sequencing data, there were more than two introns in the newly cloned gene. There was 62% homology between the part of the predicted amino acid sequence of cloned gene and CDC3 amino acid sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.234-241
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• 2012

This paper proposes a novel design methodology considering transistor layout variation. The proposed design technique is to improve the transistor's electrical characteristics without performing a circuit simulation to extract transistor layout variation. There are three advantages in the proposed method. Firstly, there is no need to change the normal design flow used in layout designs. Secondly, there is no need to perform simulation in order to extract the transistor layout variation. Thirdly, early warnings in layout design lead to decreasing the number of post layout simulations. Less post layout simulations will decrease the number of iterations in the design cycle and shorten design period. The number of bad transistors in the early design phase were reduced from 17.8% to 2.9% by applying eDRC environment for layout designers to develop Standard Cell Library.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.27-35
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• 1999

In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.

• Parasites, Hosts and Diseases
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• v.46 no.4
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• pp.209-216
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• 2008

A monoclonal antibody against Toxoplasma gondii of Tg556 clone (Tg556) blotted a 29 kDa protein, which was localized in the dense granules of tachyzoites and secreted into the parasitophorous vacuolar membrane (PVM) after infection to host cells. A cDNA fragment encoding the protein was obtained by screening a T. gondii cDNA expression library with Tg556, and the full-length was completed by 5'-RACE of 2,086 bp containing an open reading frame (ORF) of 669 bp. The ORF encoded a polypeptide of 222 amino acids homologous to the revised GRA3 but not to the first reported one. The polypeptide has 3 hydrophobic moieties of an N-terminal stop transfer sequence and 2 transmembrane domains (TMD) in posterior half of the sequence, a cytoplasmic localization motif after the second TMD and an endoplasmic reticulum (ER) retrival motif in the C-terminal end, which suggests GRA3 as a type III transmembrane protein. With the ORF of GRA3, yeast two-hybrid assay was performed in HeLa cDNA expression library, which resulted in the interaction of GRA3 with calcium modulating ligand (CAMLG), a type II transmembrane protein of ER. The specific binding of GRA3 and CAMLG was confirmed by glutathione S-transferase (GST) pull-down and immunoprecipitation assays. The localities of fluorescence transfectionally expressed from GRA3 and CAMLG plasmids were overlapped completely in HeLa cell cytoplasm. In immunofluorescence assay, GRA3 and CAMLG were shown to be co-localized in the PVM of host cells. Structural binding of PVM-inserted GRA3 to CAMLG of ER suggested the receptor-ligand of ER recruitment to PVM during the parasitism of T. gondii.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.23-32
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• 2010

In this paper, we first propose the security enhancing of authentication protocol for Hash based RFID tag, and then a digital Codec for RFID tag is designed based on the proposed authentication protocol. The protocol is based on a three-way challenge response authentication protocol between the tags and a back-end server. In order to realize a secure cryptographic authentication mechanism, we modify three types of the protocol packets which defined in the ISO/IEC 18000-3 standard. Thus active attacks such as the Man-in-the-middle and Replay attacks can be easily protected. In order to verify effectiveness of the proposed protocol, a digital Codec for RFID tag is designed using Verilog HDL, and also synthesized using Synopsys Design Compiler with Hynix $0.25\;{\mu}m$ standard-cell library. Through security analysis and comparison result, we will show that the proposed scheme has better performance in user data confidentiality, tag anonymity, Man-in-the-middle attack prevention, replay attack, forgery resistance and location tracking.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.