• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.12
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• pp.1093-1105
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• 2012

We propose an interference space reuse (ISR) algorithm for the MU-MIMO design in 3-cell downlink interference channels. Also, we provide a strategy for the adoption of the ISR scheme in the cellular network. In the multicell interference channels, the cell edge users may undergo severe interferences and their signals should be protected from the interferers for reliable transmissions. However, the intra cell users do not only experience small interferences but also they require small transmission power for stable communication. We provide a vector design algorithm based on ISR, where intra cell users are served through reusing the cell edge users' interference space. The performance enhancement reaches 20% compared to the fractional frequency reuse (FFR) scheme combined with IA through the scheduling between the cell edge users and the intra cell users. Also, it can be used to enhance the cell edge throughput when the quality of service (QoS) requirements of the intra cell users are fixed.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.55-66
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• 2016

Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

• Journal of Digital Convergence
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• v.11 no.8
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• pp.199-204
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• 2013

Computational fluid dynamics (CFD) is used to reduce number of experiments. The CFD tools are widely used for engine design and flow pattern analysis to reduce experiments. In this study the performance of a PEMFC single cell was analyzed by using STAR-CD, product of CD-ADAPCO. The effect of cell design and flow pattern on the performance of a PEMFC was analyzed with the 3-D simulation. As a result the performance of rectangular cell was the higher than that of square cell, while the flow direction scarcely affected on the performance of a PEMFC. Also the current density according to different excess ratio of air flow rate was compared and analyzed. The difference between maximum and minimum current density of flip-flow was lower than that of co-flow.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.342-351
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• 2008

In this paper, a new handover procedure for OFDM-based multi-hop relay systems is proposed to reduce the handover overhead by distinguishing inter-cell handover event from intra-cell handover event at the level of physical layer using a hierarchical design concept of preamble. A Subcell ID concept for identifying RS in a cell is proposed in the design of hierarchical manner, in addition to the existing Cell ID for identifying BS. The decision on either inter-cell handover or intra-cell handover is made by the signal quality measure of CBINR(Carrier of BS to Interference and Noise Ratio) and CRINR(Carrier of RS to Interference and Noise Ratio), provided by the hierarchical preamble. The proposed handover procedure can simplify scanning procedure and skip/simplify network re-entry procedure (capability negotiation, authorization, registration), resulting in a significant reduction of handover overhead.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.140-142
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• 2003

We have designed a SFQ (Single Flux Quantum) D2 Cell and Inverter(NOT) for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we have used Julia, XIC and Lmeter for simulations and layouts. We obtained the circuit margin of larger than $\pm$25%. After layout, we drew chip for fabrication of SFQ D2 Cell and Inverter. We connected D2 Cell and Inverter to jtl, DC/SFQ, SFQ/DC and RS flip-flop for measurement.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.20-23
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• 2009

The efficacy improvement issues in a unit discharge cell have been approached from the structural considerations. The tested cell designs include (a) a coplanar type with annular auxiliary electrode buried in barrier ribs, (b) a coplanar type with split auxiliary electrodes also burred in barrier ribs and (c) a coaxial type with a floating electrode stacked on the base electrode. From spatiotemporally resolved optical images of near-IR emission taken by a gated-ICCD camera and relative VUV emission intensity estimated by laser absorption spectroscopy, the differences in the discharge and light emission performances of those three cell types have been compared and discussed.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.156-156
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• 2009

High efficiency silicon solar cell technology based on planar technology has been improved by various kinds of process by using the wet etching process. In particular, the buried contact solar cell has been successfully studied. In the present work, a simplified process of the buried contact solar cell has been suggested to help one design effectively the high-efficiency solar cell.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.22 no.49
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• pp.67-76
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• 1999

This research presents the relationship among machining time, cycle time and demand rate in a cellular manufacturing system. The manufacturing cell produces part families by automated machines. This paper discusses the cases of increasing demand rate in an existing cell and designing cell based on the demand rate. This research developed an algorithm for decision making such as cycle time, machines and workers in order to minimize the total machine capacity and the number of workers for any given demand rate. The proposed algorithm was successfully applied for the design and operation of cell manufacturing with a good result.

• Journal of Power Electronics
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• v.15 no.3
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• pp.830-840
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• 2015

The H-bridge inverter is the fundamental power cell of the cascaded distribution static synchronous compensator (DSTATCOM). Thus, cell reliability is important to the compensation performance and stability of the overall system. The concept of the power electronics building block (PEBB) is an ideal solution for the power cell design. In this paper, an H-bridge inverter-based “plug and play” HPEBB is introduced into the main circuit and the controller to improve the compensation performance and reliability of the device. The section that discusses the main circuit primarily emphasizes the design of electrical parameters, physical structure, and thermal dissipation. The section that presents the controller part focuses on the principle of complex programmable logic device -based universal controller This section also analyzes typical reliability and anti-interference issues. The function and reliability of HPEBB are verified by experiments that are conducted on an HPEBB test-bed and on a 10 kV/± 10 Mvar DSTATCOM industrial prototype.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1132_1133
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• 2009

In this paper, a observer-based PI controller will be developed for PEM fuel cell system. Nonlinear model of PEM fuel cell system is introduced to study the controller design problems. Sliding mode observer will be designed to estimate the cathode and anode pressures of PEMFC system. And a nonlinear state observer is also designed to estimate the other states such as supply manifold pressure, Oxygen pressure, Hydrogen pressure, return manifold pressure, etc. These estimated states are used to design the observer-based PI controller. The validity of the proposed controller will be verified by using computer simulation.