• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.275-282
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• 2004

In this paper, a transcoding method that transforms MPEG-4 video bitstream coded in 30 Hz frame rate into H.264 video bitstream of 15 Hz frame rate is proposed. The block modes and motion vectors in MPEG-4 is utilized in H.264 for block mode conversion and motion vector (MV) interpolation methods. The proposed three types of MV interpolation method can be used without performing full motion estimation in H.264. The proposed transcoder reduces computation amount for full motion estimation in H.264 and provides good quality of H.264 video at low bitrates. In experimental results, the proposed methods achieves 3.2-4 times improvement in computational complexity compared to the cascaded pixel-domain transcoding, while the PSNR (peak signal to noise ratio) is degraded with 0.2-0.9dB depending on video sizes.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.1
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• pp.53-64
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• 2004

This paper proposes a monopulse beamforming network to estimate a target angle in interference conditions. The proposed system estimates the target direction of arrival (DOA) with two separate beamformings for azimuth and elevation with a planar may. The elevation is extracted from adaptive beamforming in the azimuth direction and the azimuth from adaptive beamforming in the elevation direction. Unlike conventional monopulse beamforming techniques using complex correction formulas or a cascaded architecture of an adaptive array and a mainlobe canceller, the proposed system is very efficient from the computational complexity. The advantage is from fact that the monopulse ratio of the proposed system does not depend on the adapted weights. Moreover, the proposed system can estimate the DOA of the target even for multiple mainlobe interferences since it does not need my kinds of mainlobe maintenance technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.120-127
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• 2005

The design method of the transversal filter using continuously cascaded directional couplers is presented. The coupler can be treated for a continuously varying nonuniform coupled transmission line. The design method is based on the optimum extraction of desired coupling factor by the control of null positions which are inherent to the coupling spectra pattern. In the optimization process, the improved Woodward-Lawson sampling method is applied to easily synthesize the distributed delay and weighting elements for transversal filter properties. For application, the microstrip transversal filter is fabricated and optimum dielectric overlay is introduced for the mode phase velocity compensation for non-TEM coupler nodes by using SDA(Spectral Domain Approach). Experiment results confirm the validity of the proposed method.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.23-30
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• 2010

The H.264/AVC is increasingly used in broadcast video applications such as Internet Protocol television (IPTV), digital multimedia broadcasting (DMB) because of high compression performance. But the H.264/AVC coded video can be delivered to the widespread end-user equipment for MPEG-2 after transcoding between this video standards. This paper suggests a new transcoding algorithm for H.264/AVC to MPEG-2 transcoder that uses motion vector clustering in order to reduce the complexity without loss of video quality. The proposed method is exploiting the motion information gathered during h.264 decoding stage. To reduce the search space for the MPEG-2 motion estimation, the predictive motion vector is selected with a least distortion of the candidated motion vectors. These candidate motion vectors are considering the correlation of direction and distance of motion vectors of variable blocks in H.264/AVC. And then the best predictive motion vector is refined with full-search in ${\pm}2$ pixel search area. Compared with a cascaded decoder-encoder, the proposed transcoder achieves computational complexity savings up to 64% with a similar PSNR at the constant bitrate(CBR).

• Journal of Broadcast Engineering
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• v.21 no.4
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• pp.621-629
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• 2016

This paper suggests a new structure of hybrid DRC to enhance the psychoacoustic sound quality of a conventional multiband DRC. The proposed hybrid DRC consists of two serially cascaded stages. The front stage DRC is multiband, and it compresses input based on RMS level detection, whereas, the back stage DRC is single band, and it regulates input according to peak level detection. The proposed hybrid DRC shows better loudness while suppressing distortion by clipping. The proposed algorithm was verified through MATLAB simulation, and it was implemented using an FPGA board for listening test. The test result showed that the proposed hybrid structure enhances overall psychoacoustic sound quality compared to conventional structures, which is based on only RMS or peak level detection.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.15-21
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• 1999

The scalability of optical cross-connect nodes is analyzed based on the limiting factor of transmission performance. The limiting factors considered are ASE noise accumulation and gain saturation in the optical amplifiers, and crosstalk in both wavelength multiplexers/demultiplexers and optical switches. When the wavelength multiplexer/demultiplexers crosstalk is lower than 25dB, Power Penalty is below 1dB for the cascaded transmission of 10 nodes with 4 input/output ports. When 10Gbps signals are transmitted through nodes with 4 and 16 input/output Ports, performance degradation due to switch crosstalk is dominant compared to that due to ASE noise accumulation if the switch crosstalk is larger than 30dB and 45dB, respectively. For the single stage transmission of 10Gbps signal with 21dB fiber link loss, the maximum loss of optical cross-connect nodes must be under 34dB to achieve the BER of $10^{-12}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.23-29
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• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.70-78
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• 2009

This paper addresses the analysis and the design optimization of differential interconnects for high-speed Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and trace space in differential printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, and time-domain transient simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects. We believe that the proposed approach is very helpful to optimize high-speed differential FPCB interconnects for LVDS applications.