• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.35-40
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• 2015

In this study, an n-ZnO/p-Si heterojunction diode with embedded Ag nanoparticles was fabricated to investigate the possible improvement of light trapping via the surface plasmon resonance effect for solar cell applications. The Ag nanoparticles were fabricated by the physical sputtering method. The acquired current-voltage curves and optical absorption spectra demonstrated that the application of Ag nanoparticles in the n-ZnO/p-Si interface increased the photo current, particularly in specific wavelength regions. The results indicate that the enhancement of the photo current was caused by the surface plasmon resonance effect generated by the Ag nanoparticles. In addition, minority carrier lifetime measurements showed that the recombination losses caused by the Ag nanoparticles were negligible. These results suggest that the embedding of Ag nanoparticles is a powerful method to improve the performance of n-ZnO/p-Si heterojunction solar cells.

• Nano
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• v.13 no.11
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• pp.1850129.1-1850129.10
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• 2018

To improve the high charge carrier recombination rate and low visible light absorption of {001} facets exposed $TiO_2$ [$TiO_2(001)$] nanosheets, few-layered $MoS_2$ nanoparticles were loaded on the surfaces of $TiO_2(001)$ nanosheets by a simple photodeposition method. The photocatalytic activities towards Rhodamine B (RhB) were investigated. The results showed that the $MoS_2-TiO_2(001)$ nanocomposites exhibited much enhanced photocatalytic activities compared with the pure $TiO_2(001)$ nanosheets. At an optimal Mo/Ti molar ratio of 25%, the $MoS_2-TiO_2(001)$ nanocomposites displayed the highest photocatalytic activity, which took only 30 min to degrade 50 mL of RhB (50 mg/L). The active species in the degradation reaction were determined to be $h^+$ and $^{\bullet}OH$ according to the free radical trapping experiments. The reduced charge carrier recombination rate, enhanced visible light utilization and increased surface areas contributed to the enhanced photocatalytic performances of the 25% $MoS_2-TiO_2(001)$ nanocomposites.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.205-205
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• 2013

테라헤르쯔(terahertz: THz)파는 0.1~10 THz 의 범위로 적외선과 방송파 사이에 광대역 주파수 스펙트럼을 차지하고 있으며 직진성, 투과성, 그리고 낮은 에너지 (meV)를 가지고 있어 비 파괴적이고 무해한 장점을 지니고 있다. Ti:sapphire laser와 같은 femto-pulse source 등이 많은 발전이 되어 현재 많은 연구와 발전이 이루어지고 있다. femto-pulse source를 이용한 THz 응용에서는 높은 저항, 큰 전자 이동도, 그리고 아주 짧은 전하수명의 기판을 요구하는데 저온에서 성장한 (low-temperature grown : LT) GaAs는 격자 내에 Gallium 자리에 Arsenic이 치환 하면서 AsGa antisite가 발생하여 전하수명을 짧아지는 것을 응용하여 가장 많이 이용되고 있다. 현재 THz 응용분야에서 보다 작고 가격경쟁력이 있는 광통신을 이용한 THz photomixer등이 활발히 연구 하고 있다. 광섬유 내에서 손실과 분산이 최소값을 가지는 부분이 1.55 ${\mu}m$ 부근이고 In0.53Ga0.47As 기판을 이용하였을 때 여기에 완벽하게 만족하게 된다. 하지만 LT-InGaAs 의 경우 AsGa antisite로 인하여 carrier lifetime은 짧아지지만 높은 n-type 전하밀도를 가지게 된다. 이때 Be을 doping하여 전하밀도를 보상하여 높은 저항을 유지해야 하는데 Be의 활성화를 위해서는 열처리를 필요로 한다. 하지만 열처리를 하면 carrier lifetime이 길어지기 때문에 carrier lifetime과 저항을 적절히 조율해야 한다. 이는 물질자체의 특성이기 때문에 InGaAs는 GaAs보다 낮은 amplitude와 짧은 cut-off frequency를 가진다. 본 연구에서는 보다 높은 저항을 얻기 위하여 molecular beam epitaxy를 이용하여 semi-insulating InP:Fe 기판위에 격자 정합된 InGaAs:Be/InAlAs multi quantum well (MQW)를 온도별 ($250{\sim}400^{\circ}C$), 주기별 (50~150)로 성장을 하였고 이때 InGaAs layer의 Be doping level은 $2{\times}1018\;cm^{-3}$, Ex-situ annealing은 $550^{\circ}C$에서 10분으로 고정 하였다. THz 발생 실험에서는 InGaAs/InAlAs MQW은 4000 pA로 1,000 pA를 가지는 InGaAs epilayer보다 4배 높은 전류 신호를 얻을 수 있었고 모든 샘플이 2 THz에서 cut-off frequency를 가지고 있었다. THz 검출 실험에서는 LT-InGaAs:Be epilayer LT-InGaAs:Be/InAlAs, HT-InGaAs/InAlAs 샘플이 각각 180, 9000, 12000 pA의 전류신호를 가지고 있었고 모든 샘플이 2 THz에서 cut-off frequency를 가지고 있었다. HT-InGaAs/InAlAs MQW를 이용한 검출실험에서는 InGaAs layer가 defect free이지만 LT-InGaAs:Be/ InAlAs MQW 보다 높은 전류 신호를 얻을 수 있었다. 이는 InAlAs layer가 저항만 높이는 것뿐만 아니라 carrier trapping layer로써의 역할도 하는 것으로 사료된다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.436-439
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• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.4
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• pp.232-237
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• 2014

We have fabricated white organic light-emitting diodes (OLEDs) by co-doping of red and blue phosphorescent guest emitters into the single host layer. Tris(2-phenyl-1-quinoline) iridium(III) [$Ir(phq)_3$] and iridium(III)bis[(4,6-di-fluorophenyl)-pyridinato-$N,C^{2^{\prime}}$]picolinate (FIrpic) were used as red and blue dopants, respectively. The effects of dopant concentration on the emission, carrier conduction and external quantum efficiency characteristics of the devices were investigated. The emissions on the guest emitters were attributed to the energy transfer to the guest emitters and direct excitation by trapping of the carriers on the guest molecules. The white OLED with 5% FIrpic and 2% $Ir(phq)_3$ exhibited a maximum external quantum efficiency of 19.9% and a maximum current efficiency of 45.2 cd/A.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.257-259
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• 1987

The photoelectronic properties of CdTe films sintered with various amounts of $CdCl_2$ and $CuCl_2$ have been investigated by measurements of dark electrical resistivity, photocurrent, thermoelectric power, optical transmission and by observation of microstructure. The grain size and optical transmission of sintered CdTe films increase with increasing amount of $CdCl_2$ indicating that $CdCl_2$ acts as a sintering aid. The photoconductivity gain(A-$cm^2/W$) increases and resistivity($\Omega$-cm) decreases with increasing amount of $CuCl_2$ up to 100ppm due to the occurance of Cu-doping during sintering. The dark resistivity could be reduced farther by post heat treatments. The dark resistivity was still high($10^3{\Omega}$-cm) so that the accurate determination of the hole concentration by Hall measurement or by thermoelectric power measurement was not possible. From the analysis of electrical activation energy, however it can be concluded that the hole concentration is less than $10^{14}/cm^3$ and all grains are depleted of carrier by the trapping centers at grain boundaries.