• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.165-167
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• 2001

Emitter injection efficiency of p+/n-buffer Junction with Gaussian impurity distribution is presented. This model takes into account the variation of the carrier lifetime with injection level which allows a unified interpretation of the injection efficiency for all injection level. The injected carrier density and injection efficiency of the anode are calculated as a function of the current density with the low level lifetime as a parameter for different thicknesses of the anode. The analytical results agree well with simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.49-56
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• 1993

In this paper, we present a new lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and substrate current influence. The suggested model is applied to a different channel structured PMOSFET, dgm/gm of both SC-PMOSFET and BC-PMOSFET appear with one straigth line about Qbib, therefore, this model is independent of channel structure. The suggested model is applied to a different drain structured SC-PMOSFET. Unlike S/D structured SC-PMOSFET, dgm/gm of LDD structured SC-PMOSFET appears with one straight line about Qb, therefore, this model is dependent of drain structure.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.30-37
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• 1993

In this paper, we present a simple and general lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and gate current influence to solve a problem that that I$_{b}$ is dependent on drain structure. The suggested model is applied to a different channel, drain structured PMOSFET. For all PMOSFETs, dg$_{m}$/g$_{m}$ of PMOSFET appears with one straight line about Q$_{g}$, therefore, this model using I$_{g}$ is consistent with experiment result independently of channel, drain structure. It is, therefore, proposed that a model using I$_{g}$ has a general applicability for PMOSFET's.

• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.397-397
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• 2009

c-Si wafer에 HWCVD로 증착된 a-Si:H 박막은 초기에 낮은 passivation 특성을 가지나 열처리 공정을 통해 효과적인 passivation을 가진다. 열처리 공정은 온도와 시간에 따라 큰 차이를 보인다. 이에 열선CVD를 이용하여 n type의 c-Si 기판에 a-Si:H을 증착하여 열처리 온도에 따른 Minority carrier Lifetime를 QSSPC를 통해 passivation 특성을 측정하였다. 온도는 $150^{\circ}C{\sim}270^{\circ}C$로 변화하여 측정하였다. 또한 열처리 시간을 10분씩 증가시켜 열처리 시간에 따른 passivation을 연구, 1ms에 이르는 Minority carrier lifetime을 얻었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.200-201
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• 2008

태양전지 제작 시 반사방지막(Anti-reflection Coating)이 태양전지 효율에 미치는 영향을 알아보기 위한 실험으로 최적의 가스비를 알아보기 위하여 Plasma Enhanced Chemical Vapor Deposition(PECVD)를 이용한 Silicon nitride 증착 실험이다. SiH4 가스를 45 sccm으로 고정시킨 상태에서 NH3를 25,45,60,90,135 sccm으로 가변하여 Carrier Lifetime과 Refractive index를 측정하였다. PECVD의 조건은 기판온도 $450^{\circ}C$, Chamber 압력 1 Torr, 증착두께 $1000\AA$으로 고정하였다. 증착 후 500, 600, 700, $800^{\circ}C$로 열처리를 하고나서 Carrier Lifetime을 측정하여 열처리에 대한 효과도 알아보았다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.120-124
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• 2000

In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8$mutextrm{s}$. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.14-15
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• 2007

Proton irradiation technology was used for improvement of switching characteristics of the PT-IGBT. The proton irradiation was carried out at 5.56 MeV energy from the back side of processed wafers and at 2.39 MeV energy from the front side of the wafers. The on-state and off-state I-V characteristics and switching properties of the device were analyzed and compared with those of un-irradiated device and e-beam irradiated device which was conventional method for minority carrier lifetime reduction. The proton irradiated device by 5.56 MeV energy was superior to e-beam irradiated device for the on-state and off-state I-V characteristics, nevertheless turn-off time of proton irradiated device was superior to that of the e-beam irradiated device.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.16 no.2
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• pp.66-70
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• 2006

Various kind of structural defects are observed to be present on the oxidized surface of the silicon crystal which was previously damaged mechanically. The formation of such defects was found to depend on the amount of damage induced and the temperature of thermal oxidation. It was confirmed by the measurement of minority carrier life time that gettering capability decreases as the size of the defects increase. The strained layer which is formed due to smaller amount of damage or lower oxidation temperature believed to has higher capability of gettering over defects like dislocation loops or stacking faults.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.143-146
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• 2009

One of the most important issues of crystalline silicon solar cell is minimizing reflectance at the surface. Laser texturing is an isotropic process that will sculpt the surface of a silicon wafer, regardless of its crystallographic orientation. We investigated surface texturing process using Nd-YAG laser ($\lambda$=1064 nm) on multi-crystalline silicon wafer. Removal of slag formed after the laser process was performed using acid solution (HF : $HNO_3$ : $CH_3COOH$ : DI water). The reflectance and carrier lifetime of the samples were measured and analyzed using UV-Vis spectrophotometer and carrier lifetime tester. It was found that the minimum reflectance of the samples was 16.39% and maximum carrier life time was $21.8\;{\mu}s$.