• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.8-14
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• 2008

A fully CMOS-integrated carbon nanotube (CNT) sensor array is proposed. After the sensor chip is fabricated in commercial CMOS process, the CNTs network is formed on the top of the fabricated sensor chip through the room-temperature post-CMOS processes. When the resistance of the CNT is changed by the chemical reaction, the read-out circuit in the chip measures the charging time of the $R_{CNT}$-Capacitor. finally the information of measured frequency is converted to a digital code. The CMOS sensor chip was fabricated by standard 0.18um technology and the size of the $8{\times}8$ sensor array is $2mm{\times}2mn$. We have carried out an experiment detecting the biochemical material, glutamate, using this sensor chip. From the experiment the CMOS sensor chip shows the feasibility of sensor for the simultaneous detection of the various target materials.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.161-161
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• 2012

질화티타늄(Titanium Nitride, TiN)은 화학적 안정성이 우수하고, N/Ti 원소 비율에 따라 열전도성 및 전기전도성이 변화하는 특성을 가지고 있어서 Metal Insulator Silicon (MIS) 나 Metal Insulator Metal (MIM) capacitor의 metal electrode 물질로 적용되고 있다. $TiCl_4$와 $NH_3$ gas를 이용하여 $500^{\circ}C$ 이상의 고온 조건에서 Chemical Vapor Deposition (CVD) 법으로 TiN 박막을 증착하는 방식이 가장 널리 사용되고 있으나, TiN 박막 내의 Chlorine (Cl) 원소가 SiO2 두께와 누설전류 밀도를 증가시키는 요인으로 작용하므로 Cl의 거동 및 함량 제어를 통한 전기적인 특성의 향상 평가가 요구되고 있다[1-3]. 본 실험에서는 $SiO_2$ 위에 TiN을 적층 한 구조에서 magnetic sector type의 Secondary Ion Mass Spectrometry (SIMS)를 이용하여 Cl 원소의 검출도 개선 방법을 연구하였다. 일반적인 $Cs^+$ 이온을 이용하여 $Cl^-$ 이온을 검출할 경우에는 TiN 하부에 $SiO_2$가 존재함에 따른 charging effect와 mass interference가 발생되는 문제점이 관찰되었다. 이를 개선하기 위해 Cl과 Cs 원소가 결합된 $ClCs^+$ cluster ion을 검출하는 방법을 시도하였으나, Cl- 이온 검출 방식에 비해 오히려 낮은 검출도를 나타내었으나 Cl 원소가 속하는 halogen 족 원소의 높은 전자 친화도 특성을 이용한 $ClCs_2^+$ cluster ion을 검출하는 방법[4]을 적용한 경우에는 $ClCs^+$ 방식에 비해 검출도가 3order 개선되는 결과를 확보하였으며, 이 결과를 토대로 Cl dose ($atoms/cm^2$) 와 Rs (ohm/sq) 간의 상관 관계에 대해 고찰하고자 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.228-238
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• 2010

There is an increasing interest in research to help overcome the energy crisis that has been focused on energy storage applications in various parts of power systems. Energy storage systems are good at enhancing the reliability or improving the efficiency of a power system by creating a time gap between the generation and the consumption of power. As a contribution to the various applications of storage devices, this paper describes a novel algorithm that determines the power and storage capacity of selected energy storage devices in order to improve upon railroad system efficiency. The algorithm is also demonstrated by means of simulation studies for the Korean railroad lines now in service. A part of this novel algorithm includes the DC railroad powerflow algorithm that considers the mobility of railroad vehicles, which is necessary because the electric railroad system has a distinct distribution system where the location and power of vehicles are not fixed values. In order to derive a more accurate powerflow result, this algorithm has been designed to consider the rail voltage as well as the feeder voltage for calculating the vehicle voltage. By applying the resultant control scheme, the charging or discharging within a specific voltage boundary, energy savings and a substation voltage stabilization using storage devices are achieved at the same time.

• Applied Chemistry for Engineering
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• v.23 no.6
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• pp.515-520
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• 2012

In this review, the fabrication of silicon based memory capacitor and organic memory thin film transistors (TFTs) was discussed for their potential identification tag applications and biosensor applications. Metal or non-metal nanoparticles (NPs) could be capped with chemicals or biomolecules such as protein and oligo-DNA, and also be self-assembly monolayered on corresponding target biomolecules conjugated dielectric layers. The monolayered NPs were formed to be charging elements of a nano floating gate layer as forming organic memody deivces. In particular, the strong and selective binding events of the NPs through biomolecular interactions exhibited effective electrostatic phenomena in memory capacitors and TFTs formats. In addition, memory devices fabricated as organic thin film transistors (OTFTs) have been intensively introduced to facilitate organic electronics era on flexible substrates. The memory OTFTs could be applicable eventually to the development of new conceptual devices.

• Journal of Power Electronics
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• v.17 no.4
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• pp.849-859
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• 2017

This paper illustrates the analysis and design of a multi-resonant converter applied to an electric vehicle (EV) charger. Thanks to the notch resonant characteristic, the multi-resonant converter achieve soft switching and operate with a narrowed switching frequency range even with a wide output voltage range. These advantages make it suitable for battery charging applications. With two more resonant elements, the design of the chosen converter is more complex than the conventional LLC resonant converter. However, there is not a distinct design outline for the multi-resonant converters in existing articles. According to the analysis in this paper, the normalized notch frequency $f_{r2n}$ and the second series resonant frequency $f_{r3n}$ are more sensitive to the notch capacitor ratio q than the notch inductor ratio k. Then resonant capacitors should be well-designed before the other resonant elements. The peak gain of the converter depends mainly on the magnetizing inductor ratio $L_n$ and the normalized load Q. And it requires a smaller $L_n$ and Q to provide a sufficient voltage gain $M_{max}$ at ($V_{o\_max}$, $P_{o\_max}$). However, the primary current increases with $(L_nQ)^{-1}$, and results in a low efficiency. Then a detailed design procedure for the multi-resonant converter has been provided. A 3.3kW prototype with an output voltage range of 50V to 500V dc and a peak efficiency of 97.3 % is built to verify the design and effectiveness of the converter.

• Journal of the Korean Solar Energy Society
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• v.33 no.4
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• pp.23-30
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• 2013

This paper presents the determination method of the hybrid energy storage capacity for compensating the output of wind power when disconnecting from the grid. In the wind power output compensation, a lot of charging and discharging time with lithium-ion battery will be deteriorated the life time. And also, this fluctuation will cause some problems of the power quality and power system stability. To solve these kind of problems, many researchers in the world have been studied with BESS(Battery Energy Storage System) in the wind farm. But, BESS has the limitation of its output during very short term period, this means that it is difficult to compensate the very short term output of wind farm. Using the EDLC (Electric Double Layer Capacitor), it is possible to solve the problem. Installing the battery system in the wind farm, it will be possible to decrease the total capacity of BESS consisting of HESS (Hybrid Energy Storage System). This paper shows simulation results when not only BESS is connected to wind farm but also to HESS. To verify the proposed system, results of computer simulation using PSCAD/EMTDC program with actual output data of wind farms of Jeju Island will be presented.

• ETRI Journal
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• v.41 no.2
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• pp.254-261
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• 2019

Distinct from conventional energy-harvesting (EH) technologies, such as the use of photovoltaic, piezoelectric, and thermoelectric effects, betavoltaic energy conversion can consistently generate uniform electric power, independent of environmental variations, and provide a constant output of high DC voltage, even under conditions of ultra-low-power EH. It can also dramatically reduce the energy loss incurred in the processes of voltage boosting and regulation. This study realized betavoltaic cells comprised of p-i-n junctions based on silicon carbide, fabricated through a customized semiconductor recipe, and a Ni foil plated with a Ni-63 radioisotope. The betavoltaic energy converter (BEC) includes an array of 16 parallel-connected betavoltaic cells. Experimental results demonstrate that the series and parallel connections of two BECs result in an open-circuit voltage $V_{oc}$ of 3.06 V with a short-circuit current $I_{sc}$ of 48.5 nA, and a $V_{oc}$ of 1.50 V with an $I_{sc}$ of 92.6 nA, respectively. The capacitor charging efficiency in terms of the current generated from the two series-connected BECs was measured to be approximately 90.7%.

• Journal of IKEEE
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• v.23 no.3
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• pp.994-1002
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• 2019

In this paper, we propose the development of a power conversion system for electric power take-off (e-PTO) of agricultural electric vehicles. Most e-PTOs use commercial power $220V_{AC}$. A bidirectional power conversion system having a two-stage structure consisting of a DC-DC converter and a DC-AC inverter for supplying a high output voltage using a low battery voltage of an agricultural electric vehicle is suitable. we propose a power conversion system consisting of the one-stage dual active bridge (DAB) converter and the two-stage bidirectional full bridge inverter. In addition, we propose a soft start algorithm for reducing the inrush current generated by the link capacitor charging during the initial operation. A 3kW prototype system and its corresponding algorithms have been implemented to verify its effectiveness through experiments.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.