• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.74-77
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• 2004

[ $HfO_2$ ] dielectric layers were grown on the p-type Si(100) substrate by metalorganic molecular beam epitaxy(MOMBE). Hafnium $t-butoxide[Hf(O{\cdot}t-C_4H_9)_4]$ was used as a Hf precursor and Argon gas was used as a carrier gas. The thickness of the layers was measured by scanning electron microscopy (SEM) and high-resolution transmission electron measurement(HR-TEM). The properties of the $HfO_2$ layers were evaluated by X-ray diffraction(XRD), high frequency capacitance-voltage measurement(HF C-V), current-voltage measurement(I-V), and atomic force measurement(AFM). HF C-V measurements have shown that $HfO_2$ layer grown by MOMBE has a high dielectric constant(k=19-21). The properties of $HfO_2$ films are affected by various process variables such as substrate temperature, bubbler temperature, Ar, and $O_2$ gas flows. In this paper, we examined the relationship between the $O_2/Ar$ gas ratio and the electrical properties of $HfO_2$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.242-242
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• 2010

산화 알루미늄($Al_2O_3$) 박막을 p-type Czochralski(CZ) Si 위에 Remote Plasma Atomic Layer Deposition(RPALD)을 이용하여 저온 공정으로 증착하였다. Photolithography 공정으로 grid 패턴을 형성한 후 열 증착기로 알루미늄을 증착하여 MIS-IL (Metal-Insulator-Semiconductor Inversion Layer) solar cell을 제작하였다. 반응소스로는 Trimethylaluminum (TMA)과 $O_2$를 이용하였다. $Al_2O_3$ 박막의 전기적 특성 평가를 위해 MIS capacitor를 제작하여 Capacitance-voltage (C-V), Current-voltage (I-V), Interface state density ($D_{it}$)를 평가하였으며 Solar simulator를 이용하여 MIS-IL Solar cell의 Efficiency을 측정하였다.

• 한국세라믹학회지
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• 제32권11호
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• pp.1262-1268
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• 1995

Photoelectrochemical properties of p-GaAs electrode have been investigated. I-V characteristic shows that the cathodic photocurrent is observed at -0.7 V vs. SCE. The photoresponse at near 870~880nm wavelength indicates that the photogenerated carriers contibuted to the observed current. The maximum converson efficiency of 35% is obtained for a Xe lamp light source at 400nm. In C-V relation, capacitance peaks appeared at the frequencies of 100Hz and 300Hz due to the activation of the interfacial states which exist at the energy level corresponding to the one-third of the GaAs band gap. The difference of about 1.1V between flatband potential (Vfb) from the Mott-Schottky method and onset voltage from I-V curve is observed due to the trap of carriers at the interfacial states in the boundary between GaAs and electrolyte. In case of WO3 deposited p-GaAs electrode, higher positive onset current and photocurent density are obtained. This can be explained by the fact that carriers are generated by light penetrated into the WO3 thin flm as well as p-GaAs substrate and then move into the electrolyte effectively.

• 한국진공학회지
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• 제10권1호
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• pp.51-56
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• 2001

MFISFET(Metal-ferroelectric-insulator-semiconductor-field effect transistor)에의 적용을 위한 절연체로서 CeO$_2$ 박막을 r.f. magnetron sputtering법에 의해 제조하였다. 스퍼터링시 증착개스는 Ar과 $O_2$를 사용하였으며 산소분압비에 따른 $CeO_2$박막의 결정성 및 전기적 특성에 미치는 영향을 평가하였다. p형-Si(100)기판 위에 $600^{\circ}C$에서 증착된 $CeO_2$ 박막들은(200)방향으로 우선방향성을 가지고 성장하였으며 Ar만으로 증착된 박막의 우선방향성은 증가하였으나 상대적으로 많은 하전입자와 표면 거칠기로 인해 C-V특성에서 큰 이력특성을 보였고 산소분압비가 증가함에 따라 양호한 특성을 보였다. 이것은 이동가능한 이온전하의 감소에 기인한다고 할 수 있다. Ce:O의 비는 모든 박막에서 1:2.22~2.42를 보여 산소과잉의 조성을 나타냈으며 산소분압비에 따라 제조된 박막들의 누설전류값은 100 kV/cm의 전계에서 $10^{-7}$~$10^{-8}$A의 차수를 보였다.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Bulletin of the Korean Chemical Society
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• 제29권4호
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• pp.777-781
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• 2008

In this work, silver nanoparticles-containing polyacrylonitrile (PAN) solutions in N,N-dimethylformamide (DMF) were electrospun to be webs consisting of nanofibers. The inputted voltage and PAN content in the solution were fixed at 15 kV and 10 wt.% in DMF with 10 cm of tip-to-collector distance (TCD). The PAN/Ag nanofiber webs were stabilized by oxidation at 250 ${^{\circ}C}$ for 2 h in air and carbonized at 1000 ${^{\circ}C}$ for 2 h in $N_2$. The resultant diameter distribution and morphologies of the nanofibers were evaluated by scanning electron microscope analysis. The electrochemical behaviors of the nanofiber webs were also observed by cyclic voltammetry tests. It was found that the presence of silver nanoparticles in carbon nanofiber webs led to the increase of specific capacitance and the decrease of fiber diameters.

• Journal of Korean Vacuum Science & Technology
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• 제2권1호
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• pp.25-31
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• 1998

The reliability of fluorine doped silicon oxide (SiOF) films for intermetal dielectrics in multilevel interconnections of ultra-large scale integrated circuits (ULSIs) is investigated. SiOF films were deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECRPECVD) using H-free source gases, i.e., SiF4 and O2. The effect of post plasma treatment on the moisture absorption and dielectric properties of SiOF films was carried out I terms of air exposure time, The reliability test of Cu/TiN/SiOF/Fi specimen was carried out in terms of temperature by rapid thermal annealing (RTA) in N2 ambient. After O2 plasma treatment,, no appreciable peak directly related to moisture absorption was detected. The capacitance-voltage (C-V) characteristics of the O2 plasma treated SiOF film showed that the film remained to hold the sound dielectric properties even after boiling treatment. The Cu/TiN/SiOF/Si system was found to be reliable up to $600^{\circ}C$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.130-131
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• 2006

차세대 반도체 정보기억장치로서 활발하게 연구되고 있는 나노 부유 게이트 메모리 (Nano Floating Gate Memory) 소자를 위해 필수적인 요소인 나노 크리스탈의 형성을 위하여 다양한 굴절률을 가진 실리콘 질화막 (SiNx)을 형성하고 고온 열처리 (rapid thermal annealing)를 실시하여 나노 크리스탈의 형성과 특성에 대한 연구를 진행하였다. 다양한 굴절률을 가진 실리콘 질화막을 형성한 후 나노 크리스탈의 형성을 위하여 열처리를 수행하였고, photoluminescence (PL)를 통하여 굴절률이 높은 Si-rich SiNx 박막의 고온 열처리를 수행한 실리콘 질화막으로부터 나노 크리스탈의 형성을 확인할 수 있었다. 또한 열처리한 실리콘 질화막 위에 Al을 증착하여 MIS 구조를 형성한 후 Capacitance-Voltage (C-V) 특성을 측정하였으며, $900^{\circ}C$에서 열처리한 박막에서 나노 크리스탈에 의한 메모리 효과를 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.492-499
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• 2013

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (${\Phi}_{bo}$) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The ${\Phi}_{bo}$ and the series resistance ($R_S$) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density ($N_{SS}$) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density $N_{SS}$ as determined by Terman's method is found to be $2.14{\times}10^{12}\;cm^{-2}\;eV^{-1}$ for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.