• Title/Summary/Keyword: capacitance - voltage (C-V)

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MATERIALS AND DETECTORS BASED ON GaInAs GROWN BY HYDRIDE VPE TECHNIQUE UTILIQUE UTILIZING A Ga/IN ALLOY SOURCE

  • Park, Chin-Ho;Tiothy J.Anderson
    • Journal of the Korean Vacuum Society
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    • v.4 no.S1
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    • pp.168-173
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    • 1995
  • $GaxIn{1_x}As$ epitaxial layers were grown by a simplified hydrode vapor phase epitaxy(VPE) method bsed on the utilization of Ga/In alloy as the source metal. The effects of a wide range of experimental variables(i.e.,inlet mole fraction of HCI, deposition temperature, Ga/In alloy composition) on the ternary composition and growth rate were investigated. Layers of $Ga_{0.47}In_{0.53}As$ lattice matched to InP were successfully grown from alloys containing 5 to 8 at.% Ga. These layers were used to produce state-of-the art p-i-n photodetectors having the following characteristics: dark current, $I_d$(-5V) = 10-20 nA: responsivity, R=0.84-0.86 A/W; dark current, Id(-5V)=10-20 nA; responsivity, R=0.84-0.86 A/W; capacitance, C=0.88-0.92 pF; breakdown voltage, $V_b$ >40V. This study demonstrated for the first time that a simplified hydride VPE process with a Ga/In alloy source is capable of producing device quality epitaxial layers.

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Metal Gate Electrode in SiC MOSFET (SiC MOSFET 소자에서 금속 게이트 전극의 이용)

  • Bahng, W.;Song, G.H.;Kim, N.K.;Kim, S.C.;Seo, K.S.;Kim, H.W.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.358-361
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    • 2002
  • Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

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Synthesis and Electrochemical Characterization of Porous Co3O4/RuO2 Composite (다공성 Co3O4/RuO2 복합체 합성 및 전기화학적 특성)

  • Lim, Hye-Min;Ryu, Kwang-Sun
    • Korean Journal of Materials Research
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    • v.22 no.3
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    • pp.118-122
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    • 2012
  • We synthesized porous $Co_3O_4/RuO_2$ composite using the soft template method. Cetyl trimethyl ammonium bromide (CTAB) was used to make micell as a cation surfactant. The precipitation of cobalt ion and ruthenium ion for making porosity in particles was induced by $OH^-$ ion. The porous $Co_3O_4/RuO_2$ composite was completely synthesiszed after anealing until $250^{\circ}C$ at $3^{\circ}C$/min. From the XRD ananysis, we were able to determine that the porous $Co_3O_4$/RuO2 composite was comprised of nanoparticles with low crystallinity. The shape or structure of the porous $Co_3O_4/RuO_2$ composite was studied by FE-SEM and FE-TEM. The size of the porous $Co_3O_4/RuO_2$ composite was 20~40 nm. From the FE-TEM, we were able to determine that porous cavities were formed in the composite particles. The electrochemical performance of the porous $Co_3O_4/RuO_2$ composite was measured by CV and charge-discharge methods. The specific capacitances, determined through cyclic voltammetry (CV) measurement, were ~51, ~47, ~42, and ~33 F/g at 5, 10, 20, and 50 mV/sec scan rates, respectively. The specific capacitance through charge-discharge measurement was ~63 F/g in the range of 0.0~1.0 V cutoff voltage and 50 mAh/g current density.

Study on electrical properties of BST thin film with substrates (기판에 따른 BST 박막의 전기적 특성에 관한 연구)

  • 이태일;최명률;박인철;김홍배
    • Journal of the Korean Vacuum Society
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    • v.11 no.3
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    • pp.135-140
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    • 2002
  • In this paper, We deposited the BST thin-film on p-type (100)Si, (100)MgO and MgO/Si substrates respectively using RF magnetron sputtering method. After the BST thin-fil m was deposited, we performed RTA(rapid thermal anneal) at $600^{\circ}C$, oxygen atmosphere and 1 min. In the XRD measurement, we observed the (110) $Ba_{0.5}Sr_{0.5}TiO_3$ main peak in all samples and the peak intensity increased after post annealing. Then we manufactured a capacitor using Al Electrode and measured I-V, C-V. In C-V measurement result values for each substrate, dielectric constant was calculated 120 (bare Si), 305(MgO/Si), 310(MgO) respectively. A leakage current density was present less than 1 $\mu\textrm{A/cm}^2$ at applied fields below 0.3 MV/cm. In conclusion we confirmed that MgO/Si substrates give good results for BST thin-film deposition.

Electrical characteristics and deep-level transient spectroscopy of a fast-neutron-irradiated 4H-SiC Schottky barrier diode

  • Junesic Park;Byung-Gun Park;Hani Baek;Gwang-Min Sun
    • Nuclear Engineering and Technology
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    • v.55 no.1
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    • pp.201-208
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    • 2023
  • The dependence of the electrical characteristics on the fast neutron fluence of an epitaxial 4H-SiC Schottky barrier diode (SBD) was investigated. The 30 MeV cyclotron was used for fast neutron irradiation. The neutron fluences evaluated through Monte Carlo simulation were in the 2.7 × 1011 to 1.45 × 1013 neutrons/cm2 range. Current-voltage and capacitance-voltage measurements were performed to characterize the samples by extracting the parameters of the irradiated SBDs. Neutron-induced defects in the epitaxial layer were identified and quantified using a deep-level transient spectroscopy measurement system developed at the Korea Atomic Energy Research Institute. As the neutron fluence increased from 2.7 × 1011 to 1.45 × 1013 neutrons/cm2, the concentration of the Z1/2 defects increased by approximately 20 times. The maximum defect concentration was estimated as 1.5 × 1014 cm-3 at a neutron fluence of 1.45 × 1013 neutrons/cm2.

Simple Route to High-performance and Solution-processed ZnO Thin Film Transistors Using Alkali Metal Doping

  • Kim, Yeon-Sang;Park, Si-Yun;Kim, Gyeong-Jun;Im, Geon-Hui
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.187-187
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    • 2012
  • Solution-processed metal-alloy oxides such as indium zinc oxide (IZO), indium gallium zinc oxide (IGZO) has been extensively researched due to their high electron mobility, environmental stability, optical transparency, and solution-processibility. In spite of their excellent material properties, however, there remains a challenging problem for utilizing IZO or IGZO in electronic devices: the supply shortage of indium (In). The cost of indium is high, what is more, indium is becoming more expensive and scarce and thus strategically important. Therefore, developing an alternative route to improve carrier mobility of solution-processable ZnO is critical and essential. Here, we introduce a simple route to achieve high-performance and low-temperature solution-processed ZnO thin film transistors (TFTs) by employing alkali-metal doping such as Li, Na, K or Rb. Li-doped ZnO TFTs exhibited excellent device performance with a field-effect mobility of $7.3cm^2{\cdot}V-1{\cdot}s-1$ and an on/off current ratio of more than 107. Also, in case of higher drain voltage operation (VD=60V), the field effect mobility increased up to $11.45cm^2{\cdot}V-1{\cdot}s-1$. These all alkali metal doped ZnO TFTs were fabricated at maximum process temperature as low as $300^{\circ}C$. Moreover, low-voltage operating ZnO TFTs was fabricated with the ion gel gate dielectrics. The ultra high capacitance of the ion gel gate dielectrics allowed high on-current operation at low voltage. These devices also showed excellent operational stability.

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Property Comparison of Ru-Zr Alloy Metal Gate Electrode on ZrO2 and SiO2 (ZrO2와 SiO2 절연막에 따른 Ru-Zr 금속 게이트 전극의 특성 비교)

  • Seo, Hyun-Sang;Lee, Jeong-Min;Son, Ki-Min;Hong, Shin-Nam;Lee, In-Gyu;Song, Yo-Seung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.9
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    • pp.808-812
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    • 2006
  • In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.

Nonvolatile Memory and Photovoltaic Devices Using Nanoparticles

  • Kim, Eun Kyu;Lee, Dong Uk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.79-79
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    • 2013
  • Quantum-structures with nanoparticles have been attractive for various electronic and photonic devices [1,2]. In recent, nonvolatile memories such as nano-floating gate memory (NFGM) and resistance random access memory (ReRAM) have been studied using silicides, metals, and metal oxides nanoparticles [3,4]. In this study, we fabricated nonvolatile memories with silicides (WSi2, Ti2Si, V2Si) and metal-oxide (Cu2O, Fe2O3, ZnO, SnO2, In2O3 and etc.) nanoparticles embedded in polyimide matrix, and photovoltaic device also with SiC nanoparticles. The capacitance-voltageand current-voltage data showed a threshold voltage shift as a function of write/erase voltage, which implies the carrier charging and discharging into the metal-oxide nanoparticles. We have investigated also the electrical properties of ReRAM consisted with the nanoparticles embedded in ZnO, SiO2, polyimide layer on the monolayered graphene. We will discuss what the current bistability of the nanoparticle ReRAM with monolayered graphene, which occurred as a result of fully functional operation of the nonvolatile memory device. A photovoltaic device structure with nanoparticles was fabricated and its optical properties were also studied by photoluminescence and UV-Vis absorption measurements. We will discuss a feasibility of nanoparticles to application of nonvolatile memories and photovoltaic devices.

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Physical and Electrical Characteristics of SrBi$_2$Ta$_2$O$_9$ thin Films Etched with Inductively Coupled Plasma Reactive Ion Etching System (유도결합형 플라즈마 반응성 이온식각 장치를 이용한 SrBi$_2$Ta$_2$O$_9$ 박막의 물리적, 전기적 특성)

  • 권영석;심선일;김익수;김성일;김용태;김병호;최인훈
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.4
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    • pp.11-16
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    • 2002
  • In this study, the dry etching characteristics of $SrBi_2Ta_2O_9$ (SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900$\AA$/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the $Ar/C1_2/CHF_3$ gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.

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Electrical Properties of Transformer Oils (II) (변압기유의 전기적인 특성 (II))

  • Lee, Yong-Woo;Cho, Don-Chan;Shin, Man-Seob;Lee, Soo-Won;Hong, Jin-Woong
    • Proceedings of the KIEE Conference
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    • 1995.07c
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    • pp.1123-1125
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    • 1995
  • In order to investigate the electrical properties for transformer oils, the dielectric properties and volume resistivity were made researches. To measure the characteristics of dielectric liquid, volume resistivity and dielectric loss, coaxial cylindrical liquid electrode was used, geometric capacitance was confirmed to 16[pF]. Highmegohm meter of VMG-1000 was used for measuring volume resistivity, the appling voltages were DC 100, 250, 500[V] in the temperature range of $20{\sim}100[^{\circ}C]$. Experiments for measuring the dielectric loss were performed at $20{\sim}120[^{\circ}C]$ in temperature range, $30{\sim}1.5{\times}10^5$[Hz] in frequency range and $300{\sim}1500$[mV] in voltage range and then, the result of experiment for the movement of carrier and the physical constants to contribute dielectric properties is introduced.

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