• Korean Journal of Materials Research
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• v.24 no.5
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• pp.259-265
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• 2014

$ZrO_2$ films were coated on aluminum etching foil by the sol-gel method to apply $ZrO_2$ as a dielectric material in an aluminum(Al) electrolytic capacitor. $ZrO_2$ films annealed above $450^{\circ}C$ appeared to have a tetragonal structure. The withdrawal speed during dip-coating, and the annealing temperature, influenced crack-growth in the films. The $ZrO_2$ films annealed at $500^{\circ}C$ exhibited a dielectric constant of 33 at 1 kHz. Also, uniform $ZrO_2$ tunnels formed in Al etch-pits $1{\mu}m$ in diameter. However, $ZrO_2$ film of 100-200 nm thickness showed the withstanding voltage of 15 V, which was unsuitable for a high-voltage capacitor. In order to improve the withstanding voltage, $ZrO_2$-coated Al etching foils were anodized at 300 V. After being anodized, the $Al_2O_3$ film grew in the directions of both the Al-metal matrix and the $ZrO_2$ film, and the $ZrO_2$-coated Al foil showed a withstanding voltage of 300 V. However, the capacitance of the $ZrO_2$-coated Al foil exhibited only a small increase because the thickness of the $Al_2O_3$ film was 4-5 times thicker than that of $ZrO_2$ film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.425-428
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• 1999

In this paper, the electrical properties of Pt/YMnO$_3$/Si(100) structures with difference rapid thermal annealing (RTA) treatment were investigated. YMnO$_3$films were obtained without buffer layers, introducing oxygen. A typical value of the dielectric constant was about 20 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 150kV/cm was about 1.34$\times$10$^{12}$ $\Omega$ . cm. The minimum interface state density around midgap was estimated to be about 5$\times$10$^{11}$ cm$^2$. eV.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1364-1369
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• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.41-46
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• 2002

In this work, we studied electrical characteristics and leakage current mechanism of Au/$Ta_2O_5$/Si metal-oxide-semiconductor (MOS) devices. $Ta_2O_5$ thin film (63nm) was deposited by atomic layer deposition (ALD) method at temperature of $235^{\circ}C$. The structures of the $Ta_2O_5$ thin films were examined by X-Ray Diffraction (XRD). From XRD, the structure of $Ta_2O_5$ was single phase and orthorhombic. From capacitance-voltage (C-V) analysis, the dielectric constant was 19.4. The temperature dependence of current-voltage (I-V) characteristics of $Ta_2O_5$ thin film was studied from 300 to 423 K. In ohmic region (<0.5 MVcm${-1}$), the resistivity was $2.4056{\times}10^{14}({\Omega}cm)$ at 348 K. The Schottky emission is dominant in lower temperature range from 300 to 323 K and Poole-Frenkel emission dominant in higher temperature range from 348 to 423 K.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.2
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• pp.357-362
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• 2017

Among the lithium metal oxides for asymmetric hybrid supercapacitor, $Li_4Ti_5O_{12}(LTO)$ is an emerging electrode material as zero-stain material in volume change during the with the charging and discharging processes. The pulverized LTO powder was observed to show the enhanced capacity from 120 mAh/g to 156 mAh/g at C-rate (10, 100 C). Hybrid supercapacitor module(48V, 416F) was fabricated using an asymmetric hybrid capacitor with a capacitance of 7500F. As a result of the measurement of C-rate characteristics, the module shows that the discharge time is drastically reduced at more than 50C, and the ESR and voltage drop characteristics are increased. The energy density and power density were reduced under high C-rate conditions. When designing asymmetric hybrid supercapacitor module, the C-rate and ESR should be considered As a result of measuring the 5 kw UPS, it was discharged at the current of 116A~170A during the discharge in the voltage range of 48V~30V, and the compensation time at discharge was measured to be about 33.2s. Experimental results show that it can be applied to applications related to stabilization of power quality by applying hybrid supercapacitor module.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.87-87
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• 1999

본 연구에서는 Pulsed Laser Deposition(이하 PDL)방법을 이용하여 Si기판에 (Ba,Sr)TiO3(이하 BST)박막을 MFS-FET(Metal-Ferroelectric-Semiconductor Field-effect Transistor)구조로 제조하였으며 BST박막의 강유전성이 BST 박막에 유도되는 응력에 어떤 영향을 받는지 살펴보았다. 본 연구에서는 완충막을 사용함으로써 BST박막과 완충막간의 격자부정합을 이용하여 BST박막에 강유전성을 유도하려고 하였다. 또한 MFS-FET구조의 BST박막에 유도되는 응력조절을 위하여 BST박막과 완충막의 두께를 변화하였으며 XRD를 통한 구조 분석 및 C-V test를 통한 전기적 특성을 관찰을 하였다. PLD법을 통해서 epitaxial 성장된 BST 박막에서는 Si에 epitaxial 성장된 완충막과의 격자부정합에 의한 BST박막내의 자발분극의 발생이 예상된다. 따라서, 본 연구는 강유전체의 자발분극에 의하여 발생되는 C-V 이력현상이 BST박막과 완충막과의 격자부정합에 의한 응력에 의해 발생될 것으로 예상하여, BST 박막에 유도되는 응력과 C-V 이력현상의 관계를 통하여 상온에서 상유전성을 갖는 BST가 응력에 의하여 어느 정도의 강유전성을 나타내는지를 밝히기 위해 진행되었다. 본 연구에서 사용된 완충막은 YSZ(Yttria Stabilized Zirconia)박막으로 0.4mTorrO2 분위기 하에서 600~80$0^{\circ}C$의 온도에서 증착하여 상형성을 살펴보았고 $700^{\circ}C$에서 epitaxial 성장을 확인하였으며 두께는 30~$\AA$으로 변화하였다. 또한 BST박막은 완충막과의 전압분배를 고려해 300~2000$\AA$으로 두께를 변화를 시키며 증착하였다. MFS 구조에서 Al 전극을 사용하여 완충막과 BST박막간의 두께 변화에 따른 Capacitance - Voltage(C-V) 측정을 하였으며 이를 통하여 강유전상의 특성인 C-V 이력현상을 관찰하였다. 그 결과 YSZ 박막에서는 C-V 이력현상이 나타나지 않았으며 BST 박막에서는 약 1.2V의 C-V이력현상이 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.776-780
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• 2009

In this study, the opto-electric properties of EL devices with PMN dielectric layer with variation of firing tempereature were investigated. For the PMN dielectric layer process, the paste was prepared by optimization of quantitative mixing of PMN powder, $BaTiO_3$, Glass Frit, $\alpha$-Terpineol and ethyl cellulose. The EL device stack consists of Alumina substrate ($Al_2O_3$), metallic electrode (Au), insulating layer (manufactured PMN paste), phosphor layer (ELPP- 030, ELK) and transparent electrode (ITO), which is well structure as a thick film EL device. The phase transformation properties of PMN dielectric with various firing temperatures of $150^{\circ}C$ to $850^{\circ}C$ was characterized by XRD. Also the opto-electric properties of EL devices with different firing temperature were investigated by LCR meter and spectrometer. We found the best opto-electric property was obtained at the condition of $550^{\circ}C$ firing which is 3432.96 $cd/m^2$ at 1948.3 pF Capacitance, 40 kHz Frequency, 40% Duty, Vth+330 V voltage.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.67-67
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• 2000

CeO2는 cubic 구조의 일종인 CaR2 구조를 가지고 있으며 격자상수가 Si의 격장상수와 매우 비슷하여 Si 기판위에 에피텍셜하게 성장할 수 있는 가능성이 매우 크다. 따라서 SOI(silicon-on-insulator)구조의 실현을 위하여 Si 기판위에 CeO2 박막을 에피텍셜하게 성장시키려는 많은 노력이 있어왔다. 또한 metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이의 완충층으로 사용된다. 이러한 CeO2의 응용을 위해서는 Si 기판 위에 성장된 CeO2 박막의 방위성 및 CeO2/Si 구조의 전기적 특성을 알아보는 것이 매우 중요하다. 본 연구에서는 Si(100) 기판위에 CeO2(200)방향으로 성장하는 박막과 EcO2(111) 방향으로 성장하는 박막을 rf magnetron sputtering 방법으로 증착하여 각각의 구조적, 전기적 특성을 분석하였다. RCA 방법으로 세정한 P-type Si(100)기판위에 Ce target과 O2를 사용하여 CeO2(200) 및 CeO2(111)박막을 증착하였다. 증착후 RTA(rapid thermal annealing)방법으로 95$0^{\circ}C$, O2 분위기에서 5분간 열처리를 하였다 이렇게 제작된 CeO2 박막의 구조적 특성을 XRD(x-ray diffraction)방법으로 분석하였고, Al/CeO2/Si의 MIS(metal-insulator-semiconductor)구조를 제작하여 C-V (capacitance-voltage), I-V (current-voltage) 특성을 분석하였으며 TEM(transmission electron microscopy)으로 증착된 CeO2막과 Si 기판과의 계면 특성을 연구하였다. C-V특성에 있어서 CeO2(111)/Si은 CeO2(111)의 두께가 증가함에 따라 hysteresis windows가 증가한 방면 CeO2(200)/Si은 hysteresis windows가 아주 작을뿐만 아니라 CeO2(200)의 두께가 증가하더라도 hysteresis windos가 증가하지 않았다. CeO2(111)/Si과 CeO2(200)/Si의 C-V 특성의 차이는 CeO2(111)과 CeO2(200)이 Si 기판에 의해 받은 stress의 차이와 이에 따른 defect형성의 차이에 의한 것으로 사료된다.