• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.667-670
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• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.509-510
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• 2008

본 논문은 $0.18{\mu}m$ CMOS 공정을 사용하여 2.5Gb/s CMOS CDR을 설계하였다. CML type의 논리게이트를 이용하여 보다 높은 주파수의 대역의 데이터를 복원하기 위한 위상비교기(PD)와 PD의 up과 down신호를 지연없이 루프필터(LF)에 공급하기 위한 전하점프(CP) 그리고 외부 스위치를 통해 VCO이득을 조절할 수 있는 링 타입의 VCO로 구성되었다. 또한 VCO의 부담을 줄이기 위하여 half-rate 클럭 테크닉을 사용하였다. Cadence tool을 사용하여 모의실험 및 layout을 하였다. VCO이득은 100MHz/V이고, 클릭 jitter는 rising일 때 27ps, falling일 때 32ps로 우수한 결과를 얻을 수 있었다. 테스트칩 제작은 매그나침 $0.18{\um}$ CMOS 공정을 이용하였다. 칩 사이즈는 PAD를 포함하여 $850um{\times}750um$이다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• Journal of the Korean Society of Physical Medicine
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• v.11 no.1
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• pp.45-52
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• 2016

PURPOSE: The purpose of this study was to determine the effects of balance training on balance pad and sand on balance and gait ability in stroke patients. METHODS: Sixty stroke patients were divided into a Balance Pad group(BPG, N = 20), a Sand group (SG, N = 20) and a Hard Ground group (HGG, N = 20) randomly. The subjects in the Hard Ground group stood in a comfortable position, faced a therapist, then threw a Swiss ball back and forth. They then performed balance training in which they raised and lowered their ankles while facing forward or moved objects from one table to another. The BPG performed same tasks in HGG, on an unstable surface using a balance pad. The SG performed same tasks on sand ground. All groups received training 30min per day, five times per week, for eight weeks. RESULTS: After intervention, all groups showed significant increases balance and gait components. And the BPG and the SG showed significant increase in weight distribution rate, Sway length and BBS compared with the HGG, but there was no significant difference in Cadence, Stride length among three groups. CONCLUSION: According to the results of this study, balance training on unstable surface using balance pad and sand was more effective in improving balance in stroke patients.

• Journal of International Academy of Physical Therapy Research
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• v.6 no.2
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• pp.840-845
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• 2015

Improvement in functional gait is one of treatment goals in treatment of cerebral palsy children. This study intended to examine the effects of insoles for postural correction on gait in spastic cerebral palsy patients by investigating changes in gait temporal spatial parameters. As the subjects, 15 spastic bilateral cerebral palsy patients participated in this study. Temporal spatial parameters of gait were measured using GAITRite system under three gait conditions. Bare foot gait, gait in shoes, and gait in insoles for postural correction were conducted. In order to look at differences in temporal spatial parameters according to three gait conditions, repeated one way analysis of variance was conducted. As post hoc test, Bonferroni was conducted. A significant level was set at ${\alpha}=.05$. According to the result of this study, gait velocity, cadence, step length, stride length of the left lower extremity significantly changed. When the subjects put on customized insoles for postural correction, the effect was greatest. There were no significant changes in stance time, single support time, double support time, swing % of gait, and stance % of cycle. Therefore, gait with insoles for postural correction positively influenced functional gait improvement and will be able to be usefully employed for spastic cerebral palsy children as one of gait assistance devices.

• Journal of The Korean Astronomical Society
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• v.42 no.1
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• pp.9-15
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• 2009

A necessary condition for the formation of a filament is magnetic helicity. In the present paper we seek the origin of magnetic helicity of intermediate filaments. We observed the formation of a sinistral filament at the boundary of a decaying active region using full-disk $H_{\alpha}$ images obtained from Bi Bear Solar Observatory. We have measured the rate of helicity injection during the formation of the filament using full-disk 96 minute-cadence magnetograms taken by SOHO MDI. As a result we found that 1) no significant helicity was injected around the region (polarity inversion line; PIL) of filament formation and 2) negative helicity was injected in the decaying active region. The negative sign of the injected helicity was opposite to that of the filament helicity. On the other hand, at earlier times when the associated active region emerged and grew, positive helicity was intensively injected. Our results suggest that the magnetic helicity of the intermediate filament may have originated from the helicity accumulated during the period of the growth of its associated active region.

• Physical Therapy Korea
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• v.5 no.2
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• pp.23-38
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• 1998

The objective of this study was to identify the effects of pelvic tilting exercise on gait patterns of hemiplegic patients. The subjects of this study were 31 hemiplegic in- and out-patients of the Rehabilitation Hospital, Yonsei University Medical Center, from September 24, 1997 through November 5, 1997. Pre- and post-treatment change in gait patterns were measured using a ink foot-print. The data were analyzed by the paired t-test, one-way ANOVA, and independent t-test. The findings were as follows: The difference in gait patterns between pre- and post-treatment was statistically significant, with an increase in gait velocity to 7.98 cm/sec post-treatment; an increase in cadence to 7.29 steps/min; a narrowing of the base of support to 1.33 cm; an increase in step length of 3.92 cm on the less affected side and 3.73 cm on the more affected side; an increase in stride length of 5.82 cm on the less affected side and 5.92 cm on the more affected side(statistically not significant in foot angle). In relation to sex, age, cause of stroke, and laterality of paralysis, the difference in gait patterns between pre- and post-treatment was not statistically significant. Where there was no significant difference of the effects of pelvic exercise regarding the degree of spasticity, the presence of a decrease in proprioception, and the duration of treatment. In conclusion, hemiplegic pelvic tilting exercise was found to have transmitting positive effect in improving gait patterns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.714-717
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• 2011

무선 송수신의 보급이 급속도로 확대됨에 따라 모바일 사용자는 새로운 기기를 구입해야 하는 불편을 따른다. 이에 대안으로 같은 기기로 다양한 기준주파수 보다, 낮은 주파수를 수용할 수 있는 주파수대역의 튜닝이 가능한 DCR(Direct conversion receiver) 의 필요성이 대두 되고 있다. 이에 DCR에 들어가는 저역통과필터는 다양한 기준주파수를 만족하기 위한 대역폭, 이득을 튜닝 하는데 중요한 부분을 차지하게 된다. 본 논문에서는 3차 Elliptic Gm-C Low Pass filter를 자이레이터 방식을 통해 DCR내의 Low Pass filter를 구현 하였다. 공급전압은 3.3V이고 외부에서 인가되는 튜닝전압에 의해 차단 주파수가 변화됨을 알 수 있었다. 그 결과를 통해서 레이아웃 하였으며, 설계된 회로는 COMS $0.18{\mu}m$ 설계 파라미터를 활용하여 Cadence 사의 Specter로 시뮬레이션 하였으며, Virtuso2로 레이아웃 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.9-9
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• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.14-14
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• 2010

A high voltage current sensing circuit for LED driver IC is designed and verfied by Cadence SPECTRE simulations. The current mirror pair, power and sensing MOSFETs with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side LDMOST switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35um BCD process show that current sensing is accurate with properly frequency compensated opamp.