• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.11
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• pp.1146-1152
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• 1990

Direct calculation algorithm for the nonzero elements of system matrix is suggested for a single machine connected to the infinite bus. Excitation system and power system stabilizer are included. When the system matrix is partitioned into 15 nonzero blocks, we can identify the location of nonzero elements and formula for each element. No matrix inversion and multiplication are necessary. Sensitivity coefficients with respect to controller parameters are suggested based on the structure of system matrix.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1299-1301
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• 1999

This paper describes a initial screening methods for weak line selection using sensitivity matrix. The elements of sensitivity matrix for line suceptance have 1 or -1, 0. From this property of sensitivity matrix, the eigen-sensitivity for line suceptance can be computed very simply and selected weak line for small signal stability or transient stability. The proposed algorithm is applied to small signal stability of New England 39-bus system and also applied to voltage stability of New England 30-bus system too.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.2
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• pp.111-118
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• 1990

This paper presents a new algorithm of contingency analysis and countermeasure to alleviate the line overloads for electric power systems. In this algorithm, the inverse matrix of the new Jacobian matrix when a contingency occurs, in fastly calculated using the house-holder's Inverse Matrix Modification Lamma (IMML) with the original factor table. The generation outputs are firstly adjusted to alleviate all line overloads occurred by the contingency without tripping loads. If the generation adjustment is not enough anymore to alleviate line overloads, then the control of bus injection power is recommended to quickly alleviate remaining overloads with minimum amount of load tripping and generation read-justing at the termination busbars of the overload lines. The proposed algorithm has been validated in tests on the 6 busbar test system.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.646-647
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• 2007

The topology processor uses the status of circuit breakers as input. It operates on the bus section connectivity data, which is stored in the data base, to determine the bus/branch topology of the network. This output of the topology processor forms part of the input to the state estimation or dispatcher power flow. This paper describes the development of the topology processor using matrix structure.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.1
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• pp.1-9
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• 1990

The structure of A matrix of one machine connected to the infinite bus is described for a full model. The A matrix can be partitioned to submatrices which depend on the initial operating point and do not depend on it. When the dynamic properties for several different operating points are desired, those submatrices can be obtained through simple column operation. Furthermore, the elements of A matrix can be directly calculated from the manufacturer's data. RMS quantities of the state variables for the initial operating point are used. This approach can save the labor for calculating the elements of A matrix for the dynamic stability analysis.

• Journal of Aerospace System Engineering
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• v.15 no.6
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• pp.50-58
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• 2021

Byteflight is developed based on RS-485 communication (an international standard), and it can be used as a data bus during the operation of an integrated avionics system in the latest aircraft. Therefore, the integrated avionics system can perform an effective and safe flight mission only when the accurate and seamless display of flight information, communication, and accurate functions of navigation are implemented. In this study, cause analysis and failure investigation were performed on screen abnormalities and communication interruptions due to signal interference in the Byteflight data bus of the integrated avionics system during aircraft operation. To improve signal interference between avionics units, the branch point and wiring path of the Byteflight data bus were changed, and the verification result of the improved method was also described.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.221-225
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• 1989

Direct calculation algorithm for the elements of A matrix in multimachine power systems with constant impedance loads has been suggested. Generator's rotor parameters need not be determined from the manufacturer's data. We can identify the elements of A matrix into two categories: One is related to only generator parameters, and the other is related to generator parameters, initial values, and $Z_{Bus}$ matrix.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.432-436
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• 1991

This paper presents a new algorithm for the countermeasure to alleviate without shedding system loads the line overloads due to contingency in power system. This method for relieving by line switching is based on obtaining the line outage distribution factors - the linear sensitivity factors, which give the amount of change in the power flow of each line due to the removal of same other line in the power system. These factors are made up of the elements of Bus Reactance Matrix and branch reactances. In this paper a fast algorithm and program is presented for obtaining only the required Bus Reactance elements which corresponds to a non - zero elements of Bus Admittance Matrix and elements of columns which correspond to two terminal Buses of the overloaded(monitored) line. The proposed algorithm has been validated in tests on the 6 busbar test system