• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.137-146
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• 2005

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.195-197
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• 2006

In this paper, an interface unit is designed to efficiently monitor transmission data in Controller Area Network(CAN)-based control systems. The CAN uses a serial multi master communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1Mbps. The interface unit is composed of a DSP controller which collects data on the CAN bus and transfers data to a personal computer via serial communication to save and display of interesting signals. The experimental system consists of three DSP controllers which represent electronic control units of a vehicle, an interface unit for analysing the data on the bus, and a graphic monitoring program coded on the Windows platform. The validity and the effectiveness of the proposed simple type of CAN interface unit are shown through the experimental results.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.317-320
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• 2002

Recently, AMBA(Advanced Microcontroller Bus Architecture) is used as common system bus at embedded system. In this paper, we described test method of peripheral device which is connected to AMBA according to the bus interface defined by AMBA protocol We implemented one of the APB(Advanced Peripheral Bus) peipheral module, GPIO(General Purpose Input/output), and tested its functionality as il is connected to the AMBA system.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.807-810
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• 2003

The PCI 2.2 spec introduces Delayed Transaction mechanism to improve system performance for target device with slow local bus. But this mechanism has some restriction since target device doesn't know prefetch data size. So, we propose a new mechanism, which target device prefetch exact data on local bus, to improve data rate on PCI or local interface. The simulation results showed that the proposed mechanism more improves system performance than the Delayed Transaction mechanism.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.1
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• pp.23-29
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• 2013

TCN(train communication network) standard was approved in 1999 by the IEC (IEC 61375-1) and IEEE (IEEE 1473-T) organizations to warrant a reliable train and equipment interoperability. TCN defines the set of communication vehicle buses and train buses. The MVB(multifunction vehicle bus) defines the data communication interface of equipment located in a vehicle and the WTB(wire train bus) defines the data communication interface between vehicles. The WTB and each MVB will be connected over a node acting as gateway. Also, to support applications demanding a high reliability, the standard defines a redundancy scheme in which the bus may be double-line and redundant-node implemented. In this paper we have presented protocol analysis platform for the WTB redundancy which is part of TCN system, to verify communication state of high-speed trains. As a confirmation of its validity, the technology described in this paper has been successfully applied to state monitoring and protocol verification of redundancy WTB based on TCN.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.2782-2786
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• 2011

In this paper a protocol design for bus network communication between onboard signalling system and MMI(Man Machine Interface) will be presented and illustrated. Recently, many onboard signailling systems adopt hot standby for safety reasons. Hot standby is a method of redundancy in which the primary and secondary systems run simultaneously. It is convenient to use bus network(bus topology) in a hot standby system for communication between onboard signalling system and MMI. Because bus network is the simplest way to connect multiple clients such as onboard signalling system, MMI and etc. However, there are many problems when two clients want to transmit at the same time on the same bus. A effective protocol is necessary to solve that problems. We will describes protocol design which is useful when onboard signalling systems and MMIs are connected via RS485(Bus Network).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10A
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• pp.996-1002
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• 2006

USB(Universal Serial Bus) is one of the most popular communication interfaces. When USB is used in an extended range, especially configurating In-home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of TDM (Time Division Multiplexing) so that the bottleneck of bus bandwidth can be brought. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1438-1440
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• 2005

A power control and distribution unit(PCDU) plays roles of protection of battery against overcharge by active control of solar array generated power, distribution of unregulated electrical power via controlled outlets to bus and instrument units, distribution of regulated electrical power to selected bus and instrument units, and provision of status monitoring and telecommand interface allowing the system and ground operate the power system, evaluate its performance and initiate appropriate countermeasures in case of abnormal conditions. In this work, we perform the preliminary design of a PCDU scheme for the small LEO Satellite applications. The main constitutes of the PCDU are the battery interface module, the auxiliary supply modules, solar array regulators with maximum power point tracking(MPPT) technology, heater power distribution modules, internal converter modules for regulated bus voltage generation. and instrument power distribution modules.