• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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• pp.439-449
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• 2002

This paper reviews our recent research works on the interconnection technologies in electronic packaging and assembly. At the aspect of advanced joining methods, laser-ultrasonic fluxless soldering technology was proposed. The characteristic of this technology is that the oxide film was removed through the vibration excitated by high frequency laser change in the molten solder droplet. Application researches of laser soldering technology on solder bumping of BGA packages were carried out. Furthermore, interfacial reaction between SnPb eutectic solder and Au/Ni/Cu pad during laser reflow was analyzed. At the aspect of soldered joints' reliability, the system for predicting and analyzing SMT solder joint shape and reliability(PSAR) has been designed. Optimization design method of soldered joints' structure was brought forward after the investigation of fatigue failure of RC chip devices and BGA packages under temperature cyclic conditions with FEM analysis and experimental study. At the aspect of solder alloy design, alloy design method based on quantum was proposed. The macroproperties such as melting point, wettability and strength were described by the electron parameters. In this way, a great deal of the experimental investigations was replaced, so as to realize the design and research of any kinds of solder alloys with low cost and high efficiency.

• 한국보건간호학회지
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• 제27권2호
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• pp.254-266
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• 2013

Purpose: This study examined the characteristics of in-home injuries of children in low-income families and sought to identify the factors affecting parental in-home injury prevention practices. Methods: A cross-sectional descriptive survey design was applied, using questionnaires on in-home injury characteristics in children, parental in-home injury prevention practices, parental perceptions and knowledge on childhood injuries, and the Parental Stress Index. We queried 169 parents of children less than 5years of age who were enrolled in Nutrition Plus Projects at community health centers. Results: Overall, 92.7% of children had experienced in-home injuries, with sliding crashes and bumping injuries as the most frequent type of injury. The recovery rate with a scar after injury was 26.3%. Parental practices for in-home injury prevention were higher according parental age, educational status, and previous learning experiences regarding in-home safety and injury prevention. The two most significant factors affecting parental in-home injury prevention practices were age and parental perception of childhood injuries as being controllable and preventable. Conclusions: Considering the high risk of in-home childhood injuries in low-income families, safety education and the promotion of injury prevention practices for parents are recommended. The strategy to enhance the parental perception on preventing childhood injuries needs to be addressed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.235-237
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• 2007

In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• ETRI Journal
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• 제38권6호
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• pp.1163-1171
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• 2016

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low-temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low-temperature lead-free soldering and bonding processes as a possible alternative for flex-on-flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder-on-pad process with Solder Bump Maker based on Sn58Bi for low-temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of $150^{\circ}C$ using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an $85^{\circ}C$ and 85% reliability test, and an SEM cross-sectional analysis.

• ETRI Journal
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• 제35권4호
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Smart Structures and Systems
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• 제18권2호
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• pp.293-315
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• 2016

Seismic isolation is often used in protecting mission-critical structures including hospitals, data centers, telecommunication buildings, etc. Such structures typically house vibration-sensitive equipment which has to provide continued service but may fail in case sustained accelerations during earthquakes exceed threshold limit values. Thus, peak floor acceleration is one of the two main parameters that control the design of such structures while the other one is peak base displacement since the overall safety of the structure depends on the safety of the isolation system. And in case peak base displacement exceeds the design base displacement during an earthquake, rupture and/or buckling of isolators as well as bumping against stops around the seismic gap may occur. Therefore, obtaining accurate peak floor accelerations and peak base displacement is vital. However, although nominal design values for isolation system and superstructure parameters are calculated in order to meet target peak design base displacement and peak floor accelerations, their actual values may potentially deviate from these nominal design values. In this study, the sensitivity of the seismic performance of structures equipped with linear and nonlinear seismic isolation systems to the aforementioned potential deviations is assessed in the context of a benchmark shear building under different earthquake records with near-fault and far-fault characteristics. The results put forth the degree of sensitivity of peak top floor acceleration and peak base displacement to superstructure parameters including mass, stiffness, and damping and isolation system parameters including stiffness, damping, yield strength, yield displacement, and post-yield to pre-yield stiffness ratio.

• 대한의용생체공학회:의공학회지
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• 제29권3호
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• pp.239-248
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• 2008

In this study, a new method using a capacitive sensor and an adaptive filter was proposed to deal with artifacts contaminating an oscillation signal in oscilometric blood pressure measurement. The proposed method makes use of a variation of the capacitance between an electrode fixed to a cuff and an external object to detect artifacts caused by the external object bumping into the cuff. The proposed method utilizes the adaptive filter based on linear prediction to remove the detected artifacts. The conventional method using linear interpolation and the proposed method using the adaptive filter were applied to three types of the artifact-contaminated oscillation signals(no overlap, non-consecutive overlap, and consecutive overlap between artifacts and oscillations) to compare them in terms of the artifact reduction performance. The proposed method was more robust than the conventional method in the case of consecutive overlap between artifacts and oscillations. The proposed method could be useful for measuring blood pressure in such a noisy environment that the subject is being transported.

• 마이크로전자및패키징학회지
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• 제30권3호
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• pp.11-19
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• 2023

최근 Chat GPT와 같은 인공지능 (Artificial Intelligence, AI) 기술의 급격한 발전에 따라 AI 반도체의 중요성이 강조되고 있다. AI 기술은 빅데이터 처리, 딥 러닝, 알고리즘 등의 요구사항으로 인해 대용량 데이터를 빠르게 처리할 수 있는 능력을 필요로 한다. 그러나 AI 반도체는 대규모 데이터를 처리하는 과정에서 과도한 전력 소비와 데이터 병목현상 문제가 발생한다. 반도체 전공정의 초미세공정이 물리적 한계에 도달함에 따라, AI 반도체의 연산을 위한 최신 패키징 기술이 요구되는 추세이다. 본 고에서는 AI 반도체에 적용가능한 인터포저, TSV, 범핑, Chiplet, 하이브리드 본딩 패키징 기술에 대해서 기술하였다. 이러한 기술들은 AI 반도체의 전력 효율과 연산 속도를 향상시키는데 기여할 것으로 기대된다.