• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.09a
• /
• pp.165-172
• /
• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.4
• /
• pp.759-764
• /
• 2012

Copper Pillar Tin Bump (CPTB) was investigated for high density chip interconnect technology development, which was prepared by electroplating and electro-less plating methods. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM-1250 dry film photoresist (DFR), with copper electroplating for Copper Pillar Bump (CPB) formation firstly, and then tin electro-less plating on it for control oxidation. Electric resistivity and mechanical shear strength measurements were introduced to characterize the oxidation effects and bonding process as a function of thermo-compression. Electrical resistivity increased with increasing oxidation thickness, and shear strength had maximum value with $330^{\circ}C$ and 500 N at thermo-compression process. Through the simulation work, it was proved that the CPTB decreased in its size of conduction area as time passes, however it was largely affected by the copper oxidation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.726-729
• /
• 2010

Copper Pillar Tin Bump (CPTB) was investigated for high density chip interconnect technology development, which was prepared by electroplating and electro-less plating methods. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM-1250 dry film photoresist (DFR), with copper electroplating for Copper Pillar Bump (CPB) formation firstly, and then tin electro-less plating on it for control oxidation. Electric resistivity and mechanical shear strength measurements were introduced to characterize the oxidation effects and bonding process as a function of thermo-compression. Electrical resistivity increased with increasing oxidation thickness, and shear strength had maximum value with $330^{\circ}C$ and 500 N thermo-compression process. Through the simulation work, it was proved that when the CPTB decreased in its size, it was largely affected by the copper oxidation.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.4
• /
• pp.81-86
• /
• 2003

Electromigration of Sn-3.5Ag solder bump was investigated using flip chip specimens which consisted of upper Si chip and lower Si substrate. While the resistance of the flip chip sample did not almost change until the time right before the failure, the resistivity increased abruptly at the moment when complete failure of the solder joint occurred in the flip chip sample. At current densities of $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$, the activation energy for electromigration of the Sn-3.5Ag solder bump was characterized as ∼0.7 eV. Failure of the Sn-3.5Ag solder bump occurred at the solder/UBM interface due to the formation and propagation of voids at cathode side of the solder bump.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2000.11a
• /
• pp.54-54
• /
• 2000

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1998.08a
• /
• pp.139.4-139
• /
• 1998

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.4
• /
• pp.39-46
• /
• 2003

Sn-Cu eutectic solder bump was fabricated by electroplating for flip chip and its characteristics were studied. A Si-wafer was used as a substrate and the UBM(Under Bump Metallization) of Al(400 nm)/Cu(300 nm)/Ni(400 nm)/Au(20 nm) was coated sequentially from the substrate to the top by an electron beam evaporator. The experimental results showed that the plating ratio of the Sn-Cu increased from 0.25 to 2.7 $\mu\textrm{m}$/min with the current density of 1 to 8 A/d$\m^2$. In this range of current density the plated Sn-Cu maintains its composition nearly constant level as Sn-0.9∼1.4 wt%/Cu. The solder bump of typical mushroom shape with its stem diameter of 120 $\mu\textrm{m}$ was formed through plating at 5 A/d$\m^2$ for 2 hrs. The mushroom bump changed its shape to the spherical type of 140 $\mu\textrm{m}$ diameter by air reflow at $260^{\circ}C$. The homogeneity of chemical composition for the solder bump was examined, and Sn content in the mushroom bump appears to be uneven. However, the Sn distributed more uniformly through an air reflow.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.323-327
• /
• 2004

The bubble flow from the wafer surface during plating process was studied in this paper. The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and ${\alpha}-step$. In ${\alpha}-step$ measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16.6%,\;{\pm}4%$ respectively.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.2
• /
• pp.37-45
• /
• 2008

In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at $250^{\circ}C\;and\;280^{\circ}C$, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at $125^{\circ}C$ up to 2000 hours. However, bump contact resistances slightly increased at $150^{\circ}C$ due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.

• Advances in materials Research
• /
• v.1 no.1
• /
• pp.83-92
• /
• 2012

The effect of under-bump-metallization (UBM) on electromigration was investigated at temperatures ranging from $135^{\circ}C$ to $165^{\circ}C$. The UBM structures were examined: 5-${\mu}m$-Cu/3-${\mu}m$-Ni and $5{\mu}m$ Cu. Experimental results show that the solder joint with the Cu/Ni UBM has a longer electromigration lifetime than the solder joint with the Cu UBM. Three important parameters were analyzed to explain the difference in failure time, including maximum current density, hot-spot temperature, and electromigration activation energy. The simulation and experimental results illustrate that the addition 3-${\mu}m$-Ni layer is able to reduce the maximum current density and hot-spot temperature in solder, resulting in a longer electromigration lifetime. In addition, the Ni layer changes the electromigration failure mode. With the $5{\mu}m$ Cu UBM, dissolution of Cu layer and formation of $Cu_6Sn_5$ intermetallic compounds are responsible for the electromigration failure in the joint. Yet, the failure mode changes to void formation in the interface of $Ni_3Sn_4$ and the solder for the joint with the Cu/Ni UBM. The measured activation energy is 0.85 eV and 1.06 eV for the joint with the Cu/Ni and the Cu UBM, respectively.