• The Korean Journal of Ecology
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• 제17권3호
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• pp.287-297
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• 1994

수도권에서 보고된 리기다소나무 생장감소의 원인을 밝히기 위하여 33장소의 리기다소나무 숲에서 교목의 밀도, 수령 및 토양의 물리화학적 특성을 조사하였다. 토성을 제외하고 토양의 물리적 특성들은 도심지와 전원지에서 차가 없었다. 그러나 토양의 pH값, 염기포화도 및 염기성 양이온 함량은 전원지에 비해 도심지에서 낮았지만, 수용성 Al 함량과 S함량은 그 반대였다. 도심지의 토양산성화는 산성강하물에 의한 영향으로 해석된다. 다중회귀분석 결과, 수도권에서 리기다소나무 생장은 토양의 가비중<토양의 Al 함량<교목의 밀도<토양의 Mg 함량<수령의 순으로 영향이 컸다. 결론적으로 수도권에서 리기다소나무 생장의 감소는 1차적으로 토양산성화가 주요한 요인이었을 것으로 판단된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.95-102
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• 2001

Hafnium oxide thin films for gate dielectric were deposited at $300^{\circ}C$ on p-type Si (100) substrates by plasma enhanced chemical vapor deposition (PECVD) and annealed in $O_2$ and $N_2$ ambient at various temperatures. The effect of hydrogen treatment in 4% $H_2$ at $350^{\circ}C$ for 30 min on the electrical properties of $HfO_2$for gate dielectric was investigated. The flat-band voltage shifts of $HfO_2$capacitors annealed in $O_2$ambient are larger than those in $N_2$ambient because samples annealed in high oxygen partial pressure produces the effective negative charges in films. The oxygen loss in $HfO_2$films was expected in forming gas annealed samples and decreased the excessive oxygen contents in films as-deposited and annealed in $O_2$ or $N_2$ambient. The CET of films after hydrogen forming gas anneal almost did not vary compared with that before hydrogen gas anneal. Hysteresis of $HfO_2$films abruptly decreased by hydrogen forming gas anneal because hysteresis in C-V characteristics depends on the bulk effect rather than $HfO_2$/Si interface. The lower trap densities of films annealed in $O_2$ambient than those in $N_2$were due to the composition of interfacial layer becoming closer to $SiO_2$with increasing oxygen partial pressure. Hydrogen forming gas anneal at $350^{\circ}C$ for samples annealed at various temperatures in $O_2$and $N_2$ambient plays critical role in decreasing interface trap densities at the Si/$SiO_2$ interface. However, effect of forming gas anneal was almost disappeared for samples annealed at high temperature (about $800^{\circ}C$) in $O_2$ or $N_2$ambient.

• 한국산학기술학회논문지
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• 제16권3호
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• pp.2314-2320
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• 2015

MBR (Membrane Bio-Reactor) 공정은 막 오염을 해결하기 위해 막대한 에너지 소비를 하는 공정으로 알려져 있다. 이를 해결하기 위한 일환으로 전기응집 기술을 MBR에 적용하는 시도가 보고되고 있다. 본 연구에서는 전류밀도를 변화시켜가며 활성슬러지의 막 여과를 수행하여 전기응집이 막 오염 저감에 미치는 영향과 메커니즘을 파악하고자 하였다. 활성슬러지 혼합액을 전기응집한 후 회분식교반셀로 분리 막의 여과성능을 평가하였다. 전류밀도(A/m2)를 10에서 40으로 증가시켰을 때 총 오염 저항 (Rc+Rf) 값이 18%에서 79%까지 감소하여 전기응집으로 인해 분리 막의 여과성능이 향상됨을 확인할 수 있었다. 전기응집 전후로 유기물 농도와 활성슬러지 입도분포 변화는 거의 일어나지 않았다. 여과 성능의 향상은 수산화알루미늄, Al(OH)3이 생성되어 막 표면에 부착되면서 오염물질이 쌓이게 됨을 방지하는 역할, 즉 dynamic membrane 으로 작용하였기 때문인 것으로 판단되었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.241.1-241.1
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• 2011

Numerous possible applications for $ZrO_2$ nanotubes exist such as for catalyst support structures, for sensing or for applications as a solid state electrolyte. Especially, because of a large specific surface area, high efficiency for solid oxide fuel cell (SOFC) application at low temperature can be expected for nanotublar structures in even small size. A zirconium precursor, Tetrakis (ethylmethylamino) zirconium, TEMAZr and $H_2O$ oxidant were used to deposit$ZrO_2$ thin films on an anodized aluminum oxide (AAO) templates having sub-100nm cylindrical pores by atomic layer deposition (ALD) in the temperature range of 150~250$^{\circ}C$. The crystalline structures of as-prepared and post-annealed $ZrO_2$ nanotubes were characterized by x-ray diffraction and high-resolution transmission electron microscopy. The as-prepared samples at $150^{\circ}C$ and $200^{\circ}C$ were showed amorphous, whereas a mixed phase of tetragonal, monoclinic and amorphous polymorph was observed at $250^{\circ}C$. In the bulk, zirconia remains monoclinic phase up to $1,175^{\circ}C$, however, $ZrO_2$ nanotubes were showed tetragonal phase upon post thermal treatments merely at $400^{\circ}C$. This trend may be indicative of high-curvature surfaces of nanotubes and thereby the presence of intrinsic compressive strain. The amount of amorphous structures in the mixed phase as well as as-grown $ZrO_2$ nanotubes were also gradually decreased by subsequent heat treatment.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.7-7
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• 2009

Lead telluride (PbTe) is a very promising thermoelectric material due to its narrow band gap (0.31 eV at 300 K), face-centered cubic structure and large average excitonic Bohr radius (46 nm) allowing for strong quantum confinement within a large range of size. In this work, we present the thermoelectric properties of individual single-crystalline PbTe nanowires grown by a vapor transport method. A combination of electron beam lithography and a lift-off process was utilized to fabricate inner micron-scaled Cr (5 nm)/Au (130 nm) electrodes of Rn (resistance of a near electrode), Rf (resistance of a far electrode) and a microheater connecting a PbTe nanowire on the grid of points. A plasma etching system was used to remove an oxide layer from the outer surface of the nanowires before the deposition of inner electrodes. The carrier concentration of the nanowire was estimated to be as high as $3.5{\times}10^{19}\;cm^{-3}$. The Seebeck coefficient of an individual PbTe nanowire with a radius of 68 nm was measured to be $S=-72{\mu}V/K$ at room temperature, which is about three times that of bulk PbTe at the same carrier concentration. Our results suggest that PbTe nanowires can be used for high-efficiency thermoelectric devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.356.1-356.1
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• 2014

The Isolation of few-layered transition metal dichalcogenides has mainly been performed by mechanical and chemical exfoliation with very low yields. in particular, the two-dimensional layer of molybdenum disulfide (MoS2) has recently attracted much interest due to its direct-gap property and potential application in optoelectronics and energy harvesting. However, the synthetic approach to obtain high-quality and large-area MoS2 atomic thin layers is still rare. In this account, a controlled thermal reduction-sulfurization method is used to synthesize large-MoOx thin films are first deposited on Si/SiO2 substrates, which are then sulfurized (under vacuum) at high temperatures. Samples with different thicknesses have been analyzed by Raman spectroscopy and TEM, and their photoluminescence properties have been evaluated. We demonstrated the presence of mono-, bi-, and few-layered MoS2 on as-grown samples. It is well known that the electronic structure of these materials is very sensitive to the number of layer, ranging from indirect band gap semiconductor in the bulk phase to direct band gap semiconductor in monolayers. This synthetic approach is simple, scalable, and applicable to other transition metal dichalcogenides. Meanwhile, the obtained MoS2 films are transferable to arbitrary substrates, providing great opportunities to make layered composites by stacking various atomically thin layers.

• 한국재료학회지
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• 제11권4호
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• pp.319-323
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• 2001

펄스레이저 증착법 (PLD)으로 (0001)면 사파이어 기판 위에 성장시킨 ZnO 박막의 두게 변화가 표면형상, 결정성 및 전기/광학적 특성에 미치는 효과에 대하여 조사하였다. SEM 및 XRD 분석을 통해 약 4000 의 두께에서 3차원 island들이 생성되며, 박막의 두께가 증가함에 따라 결정립의 크기가 증가하고, 결정성이 향상되었음을 알 수 있었다 상온에서의 PL 측정을 통해 두께가 증가함에 따라 ultraviolet(UV) 및 deep level emission peak의 강도가 급격히 증가함을 알 수 있었다. Hall측정 결과, 모든 박막들이 H형 전도도를 보였고, 운반자농도가 $10^{19}$ $cm^{-3}$ 이상이었으며, 두께가 증가할수록 운반자농도가 감소하여 약 4000 에서 포화되는 경향을 보였다. 따라서, 사파이어 기판 위에 증착시킨 ZnO 박막은 약 4000 의 두께에서 bulk ZnO의 특성을 나타내었다.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 센서학회지
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• 제24권1호
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• pp.15-21
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• 2015

Transparent and conductive multilayer thin films consisting of three alternating layers FZTO/Ag/$WO_3$ have been fabricated by radio-frequency (RF) sputtering for the applications as transparent conducting oxides and the structural and optical properties of the resulting films were carefully studied. The single layer fluorine doped zinc tin oxide (FZTO) and tungsten oxide ($WO_3$) films grown at room temperature are found to have an amorphous structure. Multilayer structured electrode with a few nm Ag layer embedded in FZTO/Ag/$WO_3$ (FAW) was fabricated and showed the optical transmittance of 87.60 % in the visible range (${\lambda}=380{\sim}770nm$), quite low electrical resistivity of ${\sim}10^{-5}{\Omega}cm$ and the corresponding figure of merit ($T^{10}/R_s$) is equivalent to $3.0{\times}10^{-2}{\Omega}^{-1}$. The resultant power conversion efficiency of 2.50% of the multilayer based OPV is lower than that of the reference commercial ITO. Asymmetric D/M/D multilayer is a promising transparent conducting electrode material due to its low resistivity, high transmittance, low temperature deposition and low cost components.