• 제목/요약/키워드: buffer layer

검색결과 1,097건 처리시간 0.026초

버퍼층 삽입을 통한 박막 태양전지의 고효율화 시뮬레이션 (A simulation of high efficiently thin film solar cell with buffer layer)

  • 김희중;장주연;백승신;이준신
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2011년도 추계학술대회 초록집
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    • pp.64.2-64.2
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    • 2011
  • a-Si 박막 태양전지는 a-Si:H을 유리 기판 사이에 주입해 만드는 태양전지로, 뛰어난 적용성과 경제성을 지녔으나 c-Si 태양전지에 비해 낮은 변환 효율을 보이는 단점이 있다. 변환 효율을 높이기 위한 연구 방법으로는 a-Si 박막 태양전지 단일cell 제작 시 high Bandgap을 가지는 p-layer를 사용함으로 높은 Voc와 Jsc의 향상에 기여할 수 있는데, 이 때 p-layer의 defect 증가와 activation energy 증가도 동시에 일어나 변환 효율의 증가폭을 감소시킨다. 이를 보완하기 위해 본 실험에서는 p-layer에 기존의 p-a-Si:H를 사용함과 동시에 high Bandgap의 buffer layer를 p-layer와 i-layer 사이에 삽입함으로써 그 장점을 유지하고 높은 defect과 낮은 activation energy의 영향을 최소화하였다. ASA 시뮬레이션을 통해 a-Si:H보다 high Bandgap을 가지는 a-SiOx 박막을 사용하여 p-type buffer layer의 두께를 2nm, Bandgap 2.0eV, activation energy를 0.55eV로 설정하고, i-type buffer layer의 두께를 2nm, Bandgap 1.8eV로 설정하여 삽입하였을 때 박막 태양전지의 변환 효율 10.74%를 달성할 수 있었다. (Voc=904mV, Jsc=$17.48mA/cm^2$, FF=67.97).

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PSS 상 버퍼층 종류에 따른 GaN 박막 성장 특성 비교 (GaN Film Growth Characteristics Comparison in according to the Type of Buffer Layers on PSS)

  • 이창민;강병훈;김대식;변동진
    • 한국재료학회지
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    • 제24권12호
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    • pp.645-651
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    • 2014
  • GaN is most commonly used to make LED elements. But, due to differences of the thermal expansion coefficient and lattice mismatch with sapphire, dislocations have occurred at about $109{\sim}1010/cm^2$. Generally, a low temperature GaN buffer layer is used between the GaN layer and the sapphire substrate in order to reduce the dislocation density and improve the characteristics of the thin film, and thus to increase the efficiency of the LED. Further, patterned sapphire substrate (PSS) are applied to improve the light extraction efficiency. In this experiment, using an AlN buffer layer on PSS in place of the GaN buffer layer that is used mainly to improve the properties of the GaN film, light extraction efficiency and overall properties of the thin film are improved at the same time. The AlN buffer layer was deposited by using a sputter and the AlN buffer layer thickness was determined to be 25 nm through XRD analysis after growing the GaN film at $1070^{\circ}C$ on the AlN buffer CPSS (C-plane Patterned Sapphire Substrate, AlN buffer 25 nm, 100 nm, 200 nm, 300 nm). The GaN film layer formed by applying a 2 step epitaxial lateral overgrowth (ELOG) process, and by changing temperatures ($1020{\sim}1070^{\circ}C$) and pressures (85~300 Torr). To confirm the surface morphology, we used SEM, AFM, and optical microscopy. To analyze the properties (dislocation density and crystallinity) of a thin film, we used HR-XRD and Cathodoluminescence.

이온 빔 증착법으로 제작한 NiFe/FeMn/NiFe 3층박막의 버퍼층 Si에 따른 결정성 및 교환결합세기 향상 (Enhancement of Crystallinity and Exchange Bias Field in NiFe/FeMn/NiFe Trilayer with Si Buffer Layer Fabricated by Ion-Beam Deposition)

  • 김보경;김지훈;황도근;이상석
    • 한국자기학회지
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    • 제12권4호
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    • pp.132-136
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    • 2002
  • 유리기관 위에 이온 빔 증착(ion beam deposition ; IBD)법으로 제작한 버퍼층(buffer layer) Si의 두께에 따른 [NiFe/FeMn/NiFe]3층박막의 결정성과 교환결합세기(exchange bias field ; H$_{ex}$)를 조사하였다. 버퍼층 Si는 NiFe층을 fcc(111)로 매우 우세하게 초기에 결정성장 시켰다. Si/NiFe 위의 증착된 FeMn층은 ${\gamma}$-fcc(111)구조로 성장함에 따라 안정되고 큰 H$_{ex}$를 가졌고, 버퍼 110 Oe로 거의 일정하였으며, 상부 FeMn/NiFe 이중구조의 H$_{ex}$는 300 Oe까지 증가하였다. 버퍼층이 Ta일 경우와 비교해서 Si일 때 H$_{ex}$와 결정성이 향상되었다.이 향상되었다.

PCI 익스프레스의 데이터 연결 계층에서 송신단 버퍼 관리를 위한 효과적인 방법 (An Effective Method to Manage the Transmitter's Buffer in the Data Link Layer of the PCI Express)

  • 현유진;성광수
    • 전자공학회논문지CI
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    • 제41권5호
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    • pp.9-16
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    • 2004
  • PCI 익스프레스 디바이스의 데이터 연결 계층은 전송할 패킷을 저장하고 있는 송신 버퍼와 전송하였지만 아직 타겟 디바이스로부터 승인 받지 못한 패킷을 저장하고 있는 재전송 버퍼를 가지고 있어야 한다. 이렇게 전송 버퍼와 재전송 버퍼를 구분하여 구현할 경우 전송할 패킷이 전송 버퍼에 있다 하더라도 재전송 버퍼에 여유 공간이 없다면 더 이상 패킷을 전송 할 수 없다는 단점이 있다. 본 논문에서는 한 개의 버퍼로 전송 버퍼와 재전송 버퍼를 구현하는 방법을 제안한다. 제안된 버퍼 구조에서는 필요에 따라 버퍼의 공간을 유연하게 사용할 수 있기 때문에 버퍼 사용 및 데이터 전송 효율을 향상시킬 수 있다. 모의 실험 결과 버퍼의 전체 크기가 8K 바이트일 경우 제안된 방법이 버퍼를 분리하여 사용하는 방법에 비해 데이터 전송 효율이 평균 39% 향상되었다.

BLT 박막을 이용한 MFIS 구조에서 MgO buffer layer의 영향 (Effect of the MgO buffer layer for MFIS structure using the BLT thin film)

  • 이정미;김경태;김창일
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.23-26
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    • 2003
  • The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

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사파이어 기판 위에 증착된 ZnO 박막 특성에 대한 ZnO 버퍼층의 영향 (Effect of ZnO buffer layer on the property of ZnO thin film on $Al_{2}O_{3}$ substrate)

  • 김재원;강정석;강홍성;이상렬
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 춘계학술대회 논문집 디스플레이 광소자분야
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    • pp.140-142
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    • 2003
  • ZnO thin films are demanded for device applications, so ZnO buffer layer was used to improve for good properties of ZnO thin film. In this study, the structural, electrical and optical properties of ZnO thin films deposited with various buffer thickness was investigated by X-ray diffraction (XRD), Hall measurements, Photoluminescence(PL). ZnO buffer layer and ZnO thin films on sapphire($Al_{2}O_{3}$) substrate have been deposited $200^{\circ}C$ and $400^{\circ}C$ respectively by pulsed laser deposition. It is observed the variety of lattice constant of ZnO thin film by (101) peak position shift with various buffer thickness. It is founded that ZnO thin film with buffer thickness of 20 nm was larger resistivity of 200 factor and UV/visible of 2.5 factor than that of ZnO thin films without buffer layer. ZnO thin films with buffer thickness of 20 nm have shown the most properties.

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ZnO 완충층을 이용하여 증착시킨 ZnO 박막의 특성 (Properties of ZnO Thin Films Using ZnO Buffer Layer)

  • 방규현;황득규;이동희;오민석;최원국
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.224-227
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    • 2001
  • ZnO buffer layers were used to grow ZnO films on c-plane sapphire substrates. The role of ZnO buffer layers in the growth of ZnO thin films on sapphire substrates was investigated by scanning electron microscopy, X-ray diffraction, and Photolumminescence(PL) measurements. At the optimized ZnO buffer layer thickness of 100 $\AA$, FWHM of $\theta$ -rocking curve of ZnO thin films was minimized to 0.73 degrees and room temperature PL spectra showed that deep level emission was not hardly seen. The optimization of the ZnO buffer layer thickness resulted in improvements of the surface morphology and crystalline quality of ZnO thin films.

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Efficient organic light-emitting diodes with Teflon buffer layer

  • Zhang, Deqiang;Gao, Yudi;Wang, Liduo;Qiu, Yong
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.269-271
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    • 2004
  • In this report, high-performance organic light-emitting diodes (OLEDs) with polytetrafluoroethylene (Teflon) buffer layer are demonstrated. Compared with conventional buffer layer, copper phthalocaynine (CuPc), Teflon film shows lower absorption in the wavelength from 200nm to 800nm The OLEDs with Teflon and CuPc buffer layer were fabricated under same conditions, and the device performances were compared. The results indicate that when the thickness of Teflon is 1.5nm, the performance of OLEDs is greatly enhanced with an efficiency of 9.0cd/A at the current density of 100mA/$cm^2$, while the device with an optimized 30-nm-thick CuPc buffer layer only shows an efficiency of6.4cd/A at the same current density.

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Selective N+ 버퍼층을 갖는 latch up 억제를 위한 새로운 IGBT 구조 (A new IGBT structure for suppression of latch up with selective N+ buffer layer)

  • 김두영;이병훈;최연익;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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    • pp.240-242
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    • 1993
  • A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

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Characteristics of ZnO Films Deposited on Poly 3C-SiC Buffer Layer by Sol-Gel Method

  • Phan, Duy-Thach;Chung, Gwiy-Sang
    • Transactions on Electrical and Electronic Materials
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    • 제12권3호
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    • pp.102-105
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    • 2011
  • This work describes the characteristics of zinc oxide (ZnO) thin films formed on a polycrystalline (poly) 3C-SiC buffer layer using a sol-gel process. The deposited ZnO films were characterized using X-ray diffraction, scanning electron microscopy, and photoluminescence (PL) spectra. ZnO thin films grown on the poly 3C-SiC buffer layer had a nanoparticle structure and porous film. The effects of post-annealing on ZnO film were also studied. The PL spectra at room temperature confirmed the crystal quality and optical properties of ZnO thin films formed on the 3C-SiC buffer layer were improved due to close lattice mismatch in the ZnO/3C-SiC interface.