• 전력전자학회논문지
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• 제27권2호
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2020년도 전력전자학술대회
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• pp.160-162
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• 2020

A control technique for the auxiliary buck/boost converter is proposed herein to improve the load transient response of the buck converter. The proposed technique improves the system efficiency by enabling the soft switching operation of the auxiliary converter. The design guidelines for achieving capacitor charge balance for the output capacitor during the transient are also presented herein. The experimental results revealed that the output voltage undershoot and settling time during the load step-up transient were 40 mV and 14 ㎲, respectively, and the output voltage overshoot and settling time during the load step-down transient were 35 mV and 21 ㎲, respectively. The performance and effectiveness of the proposed technique were experimentally verified using a prototype buck converter with a 15-V input, 3.3-V output, and 200-kHz switching frequency.

• IEIE Transactions on Smart Processing and Computing
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• 제4권5호
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.24-31
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• 2008

최근 휴대용 멀티미디어 기기에 있어서 파워 컨버터 블록이 매우 중요한 블록으로 부각되고 있다. 본 논문에서는 휴대 기기를 위한 고성능 DC-DC buck 컨버터를 설계하였다. DC-DC buck 컨버터의 컨트롤러에는 전류를 이용한 컨트롤 방법을 사용하였다. 설계된 전류 방식 DC-DC buck 컨버터는 standard $0.18{\mu}m$ 공정을 통하여 칩으로 제작 되었고, 전체 칩의 크기는 $1.2mm^2$이다. 제작된 칩은 $1\sim1.5MHz$의 주파수에서 동작 하였고, 최대 400mA의 부하 전류를 구동할 수 있다. 또한 컨버터의 최대 변환 효율은 86%이다.

• 전력전자학회논문지
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• 제12권5호
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• pp.394-399
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• 2007

본 논문에서는 소프트 스위칭에 의한 새로운 고효율의 벅-부스트 DC-DC 컨버터에 대해 연구된다. 제안된 벅-부스트 컨버터는 기존의 벅-부스트 DC-DC 컨버터에서 문제가 되는 제어용 스위치의 스위칭 손실증대를 해결하기 위해 새로운 소프트 스위칭 기법이 적용된다. 소프트 스위칭 회로는 구조적으로 기존의 컨버터에 사용되는 벅-부스트용 인덕터와 스너버 회로를 변형 설계한 구조로써 회로구성이 간단하다. 제안된 컨버터에 사용된 제어스위치들은 부분공진의 동작에 의해 소프트 스위칭을 이룬다. 또한 컨버터의 출력전압은 제어스위치의 PWM 제어에 의해 조정되고 벅-부스트용 인덕터에 흐르는 전류는 불연속모드로 제어되어 제어회로와 제어기법이 간단한 장점이 주어진다. 제안된 벅-부스트 컨버터는 기존의 벅-부스트 컨버터와 비교되어 해석되고 컴퓨터 시뮬레이션과 실험을 통해 그 해석적 타당성이 입증된다.

• Journal of Power Electronics
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• 제17권5호
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• Journal of Power Electronics
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• 제16권6호
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• 대한전자공학회논문지SD
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• 제48권6호
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• pp.25-32
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• 2011

본 논문에서는 휴대기기를 위한 고효율 전류구동방식의 DC-DC 벅 변환기를 제안한다. 제안된 전류구동방식의 DC-DC 컨버터는 파워스위치의 전도손실을 최소화하는 적응형 사구간 제어기법을 적용하여 부하전류에 따라 효율을 2~5%이상 향상시킨다. 설계된 DC-DC 벅 변환기는 0.35${\mu}m$ CMOS공정을 이용하여 칩으로 제작 되었으며, 전체 칩의 크기는 0.97$mm^2$이다. 제작된 칩의 입력전압범위는 2.5V~3.3V이고, 출력전압은 1.8V이며 리플전압은 10mV이하로 나타내고 있다. 최대 500mA의 부하 전류에서 구동할 수 있도록 설계 하였고, 200mA에서 최대 93%의 전력효율을 나타내고 있다.

• 전기전자학회논문지
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• 제15권4호
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• pp.319-323
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• 2011

본 논문에서는 Mobile 기기의 다양한 기능을 지원하기 위해 사용되는 내부 회로들의 낮은 전압 레벨을 지원하기위해 가장 널리 사용되는 SMPS(Switch Mode Power Supply)방식의 Buck converter를 설계한다. 제안된 Buck converter는 넓은 부하 영역에서 높은 효율을 가지는 것을 목적으로 일반적인 구동 방식인 PWM (Pulse Width Modulation)Mode의 고 효율 저 리플 특성 구현 외에 PFM(Pulse Frequency Modulation) Mode를 적용하여 낮은부하 조건 혹은 부하를 사용하지 않는 대기 시간에서도 고 효율 저 리플 특성을 가지는 Dual mode synchronous buck converter를 설계한다. 이를 위해 본 논문에서는 부하 변동 시에 PWM - PFM Mode로의 효율적인 변환방법 및 저 리플 특성을 위한 방법을 제안한다. 또한 제안된 IC는 Mobile 기기에 부합하는 입력 전압 범위 2.5V-5V를 가지며, 2.5Mhz의 높은 주파수로 동작하여 리플 특성이 양호하고 집적화가 유리하다. 고효율을 위하여 Synchronous Type 설계 및 Dynamic Control 방식을 적용하였다. 보호 기능으로는 회로 동작의 초기 시에 발생하는 Inrush Current를 방지하기 위한 Soft start function 외에 Current limit, Thermal shutdown function, UVLO 회로가 내장되어 신뢰성을 높였다.