• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.3
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• pp.32-38
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• 2006

During stereolithography processes, the shape errors such as curl distortion and distortion of side face are generated due to the shrinkage of liquid resins. In this study, the effects of dimension of part and structure of supports on the shape error are examined. Cubic specimens which have different thicknesses are manufactured and their deformations are measured with CMM. Thicker part generates smaller curl distortion of top face and larger of bottom face. Also thicker part generates larger distortion of side face until part thickness increases to about 20mm. Larger stiffness of supports which is obtained by shorter spacing of the supports and line type contact instead of point type contact generates smaller shape error of the part.

• Transactions of Materials Processing
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• v.12 no.4
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• pp.370-375
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• 2003

Determination of the interface heat transfer coefficient was investigated in non-isothermal bulk forming of glass-coated Ti-6Al-4V. FE analysis and experiments were conducted. Equipment consisting of AISI Hl3 die was instrumented with thermocouples located at sub-surface of the bottom die. Die temperature changes were investigated in related to the process variables such as reduction, lubricant and initial die temperature. The calibration approach based on heat conduction and FE analysis using an inverse algorithm were used to evaluate the interface heat transfer between graphite-lubricated die and glass-coated workpiece. The coefficients determined were affected mainly by the contact pressure. The validation of the coefficients was made by the comparison between experimental data and FE analysis results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.4
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• pp.272-275
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• 2019

We investigated the electrical characteristics of amorphous silicon-zinc-tin-oxide (a-SZTO) thin films deposited by RF-magnetron sputtering at room temperature depending on the deposition time. We fabricated a thin film transistor (TFT) with a bottom gate structure and various channel thicknesses. With increasing channel thickness, the threshold voltage shifted negatively from -0.44 V to -2.18 V, the on current ($I_{on}$) and field effect mobility (${\mu}_{FE}$) increased because of increasing carrier concentration. The a-SZTO film was fabricated and analyzed in terms of the contact resistance and channel resistance. In this study, the transmission line method (TLM) was adopted and investigated. With increasing channel thickness, the contact resistance and sheet resistance both decreased.

• Proceedings of the Korean Geotechical Society Conference
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• 2006.03a
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• pp.530-535
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• 2006

The Pusan clays are soft and thick deposits and in some places, they reach even up to 50-70m. So, the pile foundations are inevitable in almost all cases. But they are significantly expansive when the length of the pile reaches about 70m. In this study, a comprehensive parametric study has been carried out in order to reduce the pile length and number of piles required in turn the cost of the foundation for particular building. A belled shaft pile has been optimized for a typical soil profile using the PLAXIS (FEM code). These results have shown a new direction of the pile foundation in Pusan, Korea. The results including the variation of contact pressures at the bottom of the bell, optimization of the angle of the bell and height of the bell in terms of the diameter of the shaft. And also, the design curves have been generated so that they can be directly used for design of belled shaft foundations. However, the structural strength criterion is being checked in the concerned laboratory.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1178-1181
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• 2006

We fabricated a flexible OTFT(organic thin film transistor) backplane for the electrophoretic display. The backplane was composed of $128{\times}96pixels$ on the Polyethylene Naphthalate substrate in which each pixel had one OTFT. The OTFTs employed bottom contact structure and used the cross-linked polyvinylphenol for gate insulator and pentacene for active layer

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.428-430
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• 2009

We fabricated flexible OTFT-backplanes with combining printing technique and conventional photolithography process for the electrophoretic display(EPD). The active area size of backplane was 6" in diagonal direction and consisted of $192{\times}150$ pixels, containing 1 OTFT employed bottom contact structure and 1 capacitance in each pixel.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.875-877
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• 2007

Zinc tin oxide (ZTO) sol-gel solution was synthesized for ink-jet printable semiconducting ink. Bottom-contact type TFT was produced by printing the ZTO layer between the source and drain electrodes. The transistor involving the ink-jet printed ZTO had the $mobility\;{\sim}\;0.01\;cm^2V^{-1}s^{-1}$. We demonstrated the direct-writing of semiconducting oxide for solution processed TFT fabrication.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.159-161
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• 2007

We fabricated flexible OTFT-backplanes for the electrophoretic display(EPD). The OTFTs employed bottom contact structure on PEN substrate and used the cross-linked polyvinylphenol for gate insulator, pentacene for active layer. Especially, we used PVA/Acryl double layers for passivation of backplane as well as for pixel dielectric layer between backplane and EPD panel. The OTFT-EPD panel worked successfully anddemonstrated to display some patterns.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.102-108
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• 2013

In manufacturing of solution-processed organic electronic devices, a spin coating method is frequently used, but which has a big problem. Solvent in a solution has a decisive effect such as physical and chemical damage for successive solution-based film deposition. Such a severe damage by solvent restricts for fabricating building blocks of multi-layered films from solutions. In this work, it will be shown that a proper combination of well-known solvents gives a chance to fabricate multi-layered film, also this new method was applied to make organic field effect transistor. Two types of bottom gate, bottom contact transistors were fabricated, one of which is fabricated by conventional single spin coating method, the other fabricated by double spin coating method. Compared with the electrical characteristics in a single spin coated transistor, the leakage current between source and gate electrode was decreased, ON state current was increased, and the extracted saturation mobility was multiplied more than 2.7 time for double spin coated transistors. It is suggested that the multiple coated gate dielectric structure is more desirable for high performance organic ferroelectric field effect transistors.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1317-1319
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• 2005

Bottom contact pentacene organic thin-film transistors are fabricated at three different substrate temperatures, $70^{\circ}C$, $80^{\circ}C$ and $90^{\circ}C$. The maximum effective mobility was obtained at $80^{\circ}C$. The contact resistance was extracted by applying two different methods, TLM method and channel-resistance method, and the value shows the minimum at $80^{\circ}C$, which is thought to be the important reason for the best performance.