• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2128-2131
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• 2003

We present an efficient algorithm for skew correction of business card images obtained by a PDA camera. The proposed method is composed of four parts: block adaptive binarization (BAB), stripe generation, skew angle calculation, and image rotation. In the BAB, an input image is binarized block by block so as to lessen the effects of irregular illumination and shadows over the input image. In the stripe generation, character string clusters are generated merging character strings and their inter-spaces, and then only clusters useful for skew angle calculation are output as stripes. In the skew angle calculation, the direction angles of the stripes are calculated using their central moments and then the skew angle of the input image is determined averaging the direction angles. In the image rotation, the input image is rotated by the skew angle. Experimental results shows that the proposed method yields correction rates of 97％ for business card images.

• Science of Emotion and Sensibility
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• v.5 no.3
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• pp.21-28
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• 2002

In order to reflect emotion and sensibility of consumers to textile pattern design, the effect of design elements of block stripe pattern on sensitivity was investigated. The stimuli were manipulated with 4 design elements of value difference (3 levels), arrangement (2 levels), width (2 levels) and interval (3 levels). Among the 36 combinations, 27 stimuli, which showed independent sensibility results in the pretest, were adopted as final stimuli. Male and female university students (n=30) evaluated each sensibility subjectively using a questionnaire developed for this study. The effect of design elements on 12 sensibility dimensions drawn by factor analysis and the relationships between the physical quantities of each stimulus and the sensibilities were investigated. As the results of ANOVA for the effect of design elements on sensibility, there were more significant differences in sensibility in the orders of value difference, interval, width, and arrangement. The value difference showed the highest explanatory power. Looking at the sensibility differences according to the level of design elements, the narrower the width of the stripe, the more 'humble', 'clean', 'modern', 'simple', and 'comfortable', and the narrower the interval between stripes, the more 'impressive' and 'conservative' The smaller the value difference, the more 'luxurious', 'modern', 'humble', 'simple', 'soft', and 'clean'. Regression models to predict the 12 sensibilities showed higher values of goodness of fit except 'conservative', 'casual' and 'modern', which were all over 0.6. Based on these results, 2 design prototypes reflecting consumer's sensibility were presented.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Proceedings of the Korean Society for Emotion and Sensibility Conference
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• 2001.11a
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• pp.25-29
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• 2001

소비자 감성 분석에 근거한 블록 스트라이프 패턴(block stripe pattern)의 디자인 방법을 제안하고자 남녀 30명을 대상으로 명도, 폭, 간격이 조작된 서로 다른 27개의 블록 스트라이프 패턴의 자극물을 제시하여 감성평가를 실시하였다. Likert 척도에 의해 명도, 배열, 폭, 간격의 4가지 디자인 요소가 요인분석을 통해 도출된 12개의 감성차원에 미치는 영향을 측정하고, 물리량에 근거한 정량적 분석을 통해 감성과의 관계를 파악하였다. 이를 근거로 각각의 감성에 부합하는 명도, 배열, 폭과 간격의 디자인 요소별 물리량과 함께 디자인 요소의 물리적 변화에 따른 감성예측 회귀모형을 도출하였다. 디자인 요소 중 명도차, 간격, 폭의 순으로 디자인 요소의 물리량 변화가 유의적인 감성차를 유발하는 것으로 나타났다. 이 중 명도차는 "캐주얼한"을 제외한 모든 감성에서 감성차에 영향을 미치는 가장 설명력 높은 디자인 요소로 분석되었다. 이 결과를 토대로 각각의 감성에 부합하는 디자인 요소별 물리량과 함께 디자인 프로토타입을 제시하였다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.11
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• pp.511-518
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• 1986

An algorithm for block-decomposition of a linear, time-invariant, discrete large-scale systems is presented, based upon the matrix sign function on Z-plane. The block-decomposition is performed by defining a reference circle, a circular stripe and projection operators. Simulation study shows that the presented algorithm is very useful for multivariable control system's analysis and design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12C
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• pp.1225-1238
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• 2003

We present an efficient algorithm for skew correction of business card images obtained by a PDA (personal digital assistant) camera. The proposed method is composed of four parts: block adaptive binarization (BAB), stripe generation, skew angle calculation, and image rotation. In the BAB, an input image is binarized block by block so as to lessen the effect of irregular illumination and shadow over the input image. In the stripe generation, character string clusters are generated merging adjacent characters and their strings, and then only clusters useful for skew angle calculation are output as stripes. In the skew angle calculation, the direction angles of the stripes are calculated using their central moments and then the skew angle of the input image is determined averaging the direction angles. In the image rotation, the input image is rotated by the skew angle. Experimental results shows that the proposed method yields skew correction rates of about 93% for test images of several types of business cards acquired by a PDA under various surrounding conditions.

• The Plant Pathology Journal
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• v.29 no.1
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• pp.17-30
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• 2013

Barley stripe mosaic virus (BSMV) induces massive actin filament thickening at the infection front of infected Nicotiana benthamiana leaves. To determine the mechanisms leading to actin remodeling, fluorescent protein fusions of the BSMV triple gene block (TGB) proteins were coexpressed in cells with the actin marker DsRed: Talin. TGB ectopic expression experiments revealed that TGB3 is a major elicitor of filament thickening, that TGB2 resulted in formation of intermediate DsRed:Talin filaments, and that TGB1 alone had no obvious effects on actin filament structure. Latrunculin B (LatB) treat-ments retarded BSMV cell-to-cell movement, disrupted actin filament organization, and dramatically decreased the proportion of paired TGB3 foci appearing at the cell wall (CW). BSMV infection of transgenic plants tagged with GFP-KDEL exhibited membrane proliferation and vesicle formation that were especially evident around the nucleus. Similar membrane proliferation occurred in plants expressing TGB2 and/or TGB3, and DsRed: Talin fluorescence in these plants colocalized with the ER vesicles. TGB3 also associated with the Golgi apparatus and overlapped with cortical vesicles appearing at the cell periphery. Brefeldin A treatments disrupted Golgi and also altered vesicles at the CW, but failed to interfere with TGB CW localization. Our results indicate that actin cytoskeleton interactions are important in BSMV cell-to-cell movement and for CW localization of TGB3.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.113-121
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• 2013

In this paper, we propose a sub-pixel rendering algorithm using learning-based 2D FIR filters. The proposed algorithm consists of two stages: the learning and synthesis stages. At the learning stage, we produce the low-resolution synthesis information derived from a sufficient number of high/low resolution block pairs, and store the synthesis information into a so-called dictionary. At the synthesis stage, the best candidate block corresponding to each input high-resolution block is found in the dictionary. Next, we can finally obtain the low-resolution image by synthesizing the low-resolution block using the selected 2D FIR filter on a sub-pixel basis. On the other hand, we additionally enhance the sharpness of the output image by using pre-emphasis considering RGB stripe pattern of display. The simulation results show that the proposed algorithm can provide significantly sharper results than conventional down-sampling methods, without blur effects and aliasing.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.