• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1862-1867
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• 1999

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.473-473
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• 2000

This paper presents the 2-bit parallel algorithmic ADC using current mode for parallel method algorithm. It is operated by parallel conversion, 2-bit at each moment, and increase bit numbers by serial connection. The circuit operates in current mode. The comparison ratio can be controlled while working under mode operation. The circuit design used 0.8 ${\mu}{\textrm}{m}$ CMOS technology which capable to convert 2-bit in 50 ns, power consumed 0.786 nW, with input current 0-50 mA from 3V single supply. From simulation testing, the conversion rate is much faster than other method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.62-65
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• 1998

This paper presents a method and implementation of the parallel distributed sample scrambler(DSS) in the cell-based ATM transmission environment. In the serial processing, it requires very high speed clock because the processing clock of the serial DSS is equal with the data transmission speed. In this paper, we develop a conversion method of the serial SRG(shift register generator) to 8bit parallel realization. In this case, it has a sample data processing problem which is a character of DSS. So, a theory of correction time movement is presented to solve this problem. We has developed a ASIC using this algorithm and verified the recommendation of ITU-T, I.432.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.56-63
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• 2001

In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.231-231
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• 2004

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.232-232
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• 2004