• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.193-197
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• 2009

In this paper, we study on design of vehicle control system which is based on ${\mu}C/OS-II$, We component a electric motor drive system for simulator because the most of vehicle part use electric motor for actuator. We use the XC2287 microcontroller which is often used vehicle body controller because XC2287 guarantee high confidence and durability in vehicle industry. The electric motor control system derive PWM from general I/O port in XC2287 microcontroller. The signal is supplied at electric motor after amplifying that using driver circuit. The user control duty of PWM signal through controlling potentiometer which is connected to XC2287. through that, the user control speed of electric motor. we synchronize both input process via controlling potentiometer and PWM output process using semaphore. we verify porting of ${\mu}C/OS-II$ via experimentation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.47-52
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• 2007

This paper analyzes the output signal-to-interference-plus-noise ratio (SINR) for a multiple-input-multiple-output (MIMO) multicarrier code division multiple access (MC-CDMA) system with minium mean square error receivers in multi-cell environments. A previous work in single cell environments is extended into analysis in multi-cell environments. The use of Haar unitary code matrix for asymptotic analysis causes other cell interferences expressed with a diagonal matrix haying different diagonal values. This paper shows that other cell interferences converge to an identity matrix whose gain is expressed by only other cell interference power in mean square sense and finds asymptotic deterministic SINRs for a given other cell interference. Under the assumption that the sum of lognormal fading components is distributed by other lognormal function, we show the comparison between theoretical performances and simulations from the view point of bit error rate and present average throughput performance according to the cell radius.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.5
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• pp.843-850
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• 2016

In this paper, we propose a digital controller design process for the interleaved type of a boost PFC (Power Factor Correction) converter which can disperse the heat of the switching devices due to the interleaved topology. We establish a mathematical model of a boost PFC converter and propose a controller design method based on the root locus. The performance of the designed controller is verified by simulations. The measurement of the input voltage, inductor currents, and the converter output link voltage are needed for the control of the converter system which consists of a power unit and a control unit where a high-performance 32-bit microcontroller is used. The adjustment of A/D conversion timing is also needed to avoid high frequency noise generated when the switches on/off. It is illustrated by the real experiments that the designed control system with the properly adjusted ADC timing satisfies the given performance specifications of the interleaved boost PFC converter in the on-board slow battery charger.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.407-408
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• 2016

A drone has been popularized to such an extent as to be seen in the near parks recently. The drone refers to an unmanned aerial vehicle(UVA) which can fly and be steered by a radio wave without a pilot and it has a airplane or helicopter shape. The drone was first started to be used from military purpose, but its usage has been expanded to the private such as broadcast shooting, crop-dusting, field discovery and hobby. However the drone that we can see often in the market is expansive, hard to be repaired when it broken down and has a discomfort of the short flight time. In this paper, to solve an uncomfortable talk on the cheap ATmega128 Using (Quad copter) drone for implementation. Axes gyroscope and accelerometers mcu between posture an attitude control, communications through drone control, pid. Receiver input them into transmitter signals of movements to control drone c the programming was implemented in on the basis of language.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.109-116
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• 2018

This paper describes an area-efficient design of SHA-256 hash function that is widely used in various security protocols including digital signature, authentication code, key generation. The SHA-256 hash processor includes a padder block for padding and parsing input message, so that it can operate without software for preprocessing. Round function was designed with a 16-bit data-path that processed 64 round computations in 128 clock cycles, resulting in an optimized area per throughput (APT) performance as well as small area implementation. The SHA-256 hash processor was verified by FPGA implementation using Virtex5 device, and it was estimated that the throughput was 337 Mbps at maximum clock frequency of 116 MHz. The synthesis for ASIC implementation using a $0.18-{\mu}m$ CMOS cell library shows that it has 13,251 gate equivalents (GEs) and it can operate up to 200 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.668-675
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• 2002

This paper proposes pre-distorter combined LUT with 2ιpartition interpolation method to reduce nonlinear distortion which was caused by high PAPR and to update LUT quickly. Pre-distorted gain and phase can be found by using LUT which consisted of AM/AM and AM/PM value, and OFDM signal amplitude. The proposed 2ιpartition interpolation can accurately find predistorted gain and phase using bit shift and add component instead of increasing size of LUT which requires increasing the amount of computation. The performance of the proposed method was measured by the difference between HPA input and output characteristics by the LUT size, constellation, SER performance by the HPA, and LUT update error by the HPA characteristic changes. As a result, it is shown that when the size of the LUT is 32 and 64 for 16-QAM and 64-QAM, nonlinear distortion nearly didn't occurred.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1493-1498
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• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive filter conducted iteration algorithm. so it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1926-1940
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• 1998

This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.5C
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• pp.476-485
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• 2003

This paper proposers a preprocessing approach to improving the quality of the music produced by the EVRC(enhanced variable rate codec) which is one of the CDMA(Code Division Multiple Access) voice codecs. Since the EVRC is optimized only for speech signals, it can deteriorate the quality of the music passed through it. One of the problems with the EVRC-coded music is time-clipping, which usually occurs when subsequent frames are encoded at Rate l/8. Since the EVRC determines the bit rate for an input frame based on the long-term prediction gain, we increase the long-term prediction gain in order for the most of the frames to be encoded at Rate 1 or Rate 1/2. Experimental results show that the approach works well on music signals and the number of time-clipped frames is considerably reduced.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.439-446
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• 2004

This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760${\mu}{\textrm}{m}$*800${\mu}{\textrm}{m}$.