• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2415-2423
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• 1999

We propose a new optical method which conceals the data of authorized persons by encryption before they are stored or compared in the pattern recognition system for security systems. This proposed security system is made up of two subsystems : a proposed optical encryption system and a pattern recognition system based on the JTC which has been shown to perform well. In this system, each image of authorized persons as a reference image is stored in memory units through the proposed encryption system. And if a fingerprint image is placed in the input plane of this security system for access to a restricted area, the image is encoded by the encryption system then compared with the encrypted reference image. Therefore because the captured input image and the reference data are encrypted, it is difficult to decrypt the image if one does not know the encryption key bit stream. The basic idea is that the input image is encrypted by performing optical XOR operations with the key bit stream that is generated by digital encryption algorithms. The optical XOR operations between the key bit stream and the input image are performed by the polarization encoding method using the polarization characteristics of LCDs. The results of XOR operations which are detected by a CCD camera should be used as an input to the JTC for comparison with a data base. We have verified the idea proposed here with computer simulations and the simulation results were also shown.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.4
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• pp.25-32
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• 1997

In this paper, we propose an adaptive BTC algorithm using the characteristics of the error signals. The BTC algorithm has a avantage that it is low computational complexity, but a disadvantage that it produces the ragged edges in the reconstructed images for th esloping regions beause of coding the input with 2-level signals. Firstly, proposed methods classify the input into low, medium, and high activity blocks based on the variance of th einput. Using 1-level quantizer for low activity block, 2-level for medium, and 4-level for high, it is adaptive methods that reduce bit rates and the inherent quantization noises in the 2-level quantizer. Also, in case of processing high activity block, we propose a new quantization level allocation algorithm using the characteristics of the error signals between the original signals and the reconstructed signals used by 2-level quantizer, in oder that reduce bit rates superior to the conventional 4-level quantizer. Especially, considering the characteristics of input block, we reduce the bit rates without incurrng the visual noises.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.594-607
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• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.295-301
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• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.833-841
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• 1997

In this paper, the hybrid LB-TJW(Leaky Bucket-Triggered Jumping Window) algorithm for multimedia traffic control is proposed and its performance is evaluated and analyzed. Its architecture is composed of the peak bit rate controller and the average bit rate controller. Generally, the cell which violates the peak bit rate is discraded in LBalgorithm, and the average bit rate of JW or TJW algorithm is better than that of LB algorithm. However, the hybrid LB-TJW algorithm passes it though the network if the cell does not violate the peak bit rate. If the cell violates the peak bit rate, the hybrid LB-TJW algorithm passes it to the average bit rate controller which perforithm to monitor the average bit rate of input traffic. The TJW algorithm monitors the cell that violates the average bit rate. If the cell does not violate the average bit rare, the LB-TJW algorithm passes it through the network. As simulation results, the cell loss rate and the buffer size of the LB-TJW algorithm is reduced to half as much as those of LB algortihm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.143-146
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• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.