• 충청수학회지
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• 제31권1호
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• pp.183-191
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• 2018

This paper deals with binary ideal topological space and discuss about generalized binary closed sets and generalized kernel in the same topological space. Further it will discuss various types of characterizations of generalized binary closed sets and generalized kernel.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.479-482
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• 1998

Whether a given tree is a subgraph of the interconnection network topology is one of the important problem in parallel computing. Trees are used as the underlying structure for divide and conquer algorithms and provide the solution spaces for NP-complete problems. Complete binary trees are the basic structure among those trees. Binomial trees play an important role in broadcasting messages in parallel networks. If binomial trees can be efficiently embedded in complex binary trees, broadcasting algorithms can be effeciently performed on the interconnection networks. In this paper, we present average dilation 2 embedding of binomial trees in complete binary trees.

• Journal of applied mathematics & informatics
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• 제38권5_6호
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• pp.533-545
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• 2020

We initiate and introduce the notion of binary soft mapping, which is defined on collection of binary soft sets named as binary soft class over two initial universes U₁ and U₂ with fixed set of parameters. We also define and study the properties of binary soft images and binary soft inverse images of binary soft sets. Examples and counter examples are also given in support of presented properties. Moreover, these concepts are applied to the problem of medical diagnosis in medical expert systems.

• 대한의용생체공학회:의공학회지
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• 제26권2호
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• pp.73-86
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• 2005

We need to flatten the brain cortex to smooth surface, sphere, or 2D plane in order to view the buried sulci. The rendered 3D surface of the segmented white matter and gray matter does not have the topology of a sphere due to the partial volume effect and segmentation error. A surface without correct topology may lead to incorrect interpretation of local structural relationships and prevent cortical unfolding. Although some algorithms try to correct topology, they require heavy computation and fail to follow the deep and narrow sulci. This paper proposes a method that corrects topology of the rendered surface fast, accurately, and automatically. The proposed method removes fractions beside the main surface, fills cavities in the inside of the main surface, and removes handles in the surface. The proposed method to remove handles has three-step approach. Step 1 performs smoothing operation on the rendered surface. In Step 2, vertices of sphere are gradually deformed to the smoothed surfaces and finally to the boundary of the segmented white matter and gray matter. The Step 2 uses multi-resolutional approach to prevent the deep sulci from geometrical intersection. In Step 3, 3D binary image is constructed from the deformed sphere of Step 2 and 3D surface is regenerated from the 3D binary image to remove intersection that may happen. The experimental results show that the topology is corrected while principle sulci and gyri are preserved and the computation amount is acceptable.

• 대한기계학회논문집A
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• 제36권7호
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• pp.745-750
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• 2012

이 논문에서는 강체 메커니즘의 위상 최적설계를 위해 제안된 구속조건 힘 설계 기법(constraint force design method)을 확장하여 로프-링크(string-link)를 고려한 위상 최적설계기법을 제안한다. 기존의 메커니즘 설계이론을 이용하여 메커니즘을 구성하는 강체 링크의 길이와 조인트의 위치를 최적설계하는 것은 가능하다. 하지만 강체 메커니즘의 최적 위상을 설계하는 것은 어렵다는 것으로 알려져 있다. 강체 메커니즘의 최적 위상을 설계할 수 있는 기법인 구속조건 힘 설계 기법이 본 연구자들에 의해 제안되었다. 구속조건 힘 설계 기법은 이진수 설계 변수를 이용하여 강체 링크의 위상 최적설계를 가능하게 한다. 이번 연구에서는 강체 링크뿐만 아니라 로프-링크로 구성된 메커니즘을 위상 최적설계하기 위한 발전된 해석기법과 설계 기법을 제안한다.

• Journal of Power Electronics
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• 제19권5호
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

• 한국자동차공학회논문집
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• 제10권4호
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• pp.216-222
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• 2002

Brake Moan is a laud and strong noise occurring at any vehicle speed over 2 mph as a low frequency in below 600Hz. In this study, we targeted to shift the unstable mode that causes the brake moan from the moats frequency range to sufficiently higher frequency range to avoid the moan phenomenon. We simulated the finite element model and found out the nodes in which the brake moan occurs the most and we regarded the boundary and its relationship between the brake pad and the rotor as a spring coefficient k. With the binary set of the spring coefficient k, we finally used genetic algorithm (GA) to get the optimal topology of the brake pad and its shape to avoid the brake moan. The final result remarkably shows that genetic algorithm can be used in topology optimization procedures requiring complex eigenvalue problems.

• Steel and Composite Structures
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• 제48권5호
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• pp.583-597
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• 2023

This paper introduces a novel approach to multi-material topology optimization (MTO) targeting in-plane bi-directional functionally graded (IBFG) non-uniform thickness Reissner-Mindlin plates, employing an alternative active phase approach. The mathematical formulation integrates a first shear deformation theory (FSDT) to address compliance minimization as the objective function. Through an alternating active-phase algorithm in conjunction with the block Gauss-Seidel method, the study transforms a multi-phase topology optimization challenge with multi-volume fraction constraints into multiple binary phase sub-problems, each with a single volume fraction constraint. The investigation focuses on IBFG materials that incorporate adequate local bulk and shear moduli to enhance the precision of material interactions. Furthermore, the well-established mixed interpolation of tensorial components 4-node elements (MITC4) is harnessed to tackle shear-locking issues inherent in thin plate models. The study meticulously presents detailed mathematical formulations for IBFG plates in the MTO framework, underscored by numerous numerical examples demonstrating the method's efficiency and reliability.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제15권3호
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• pp.208-215
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• 2015

Since upper and lower approximations could be induced from the rough set structures, rough sets are considered as approximations. The concept of fuzzy rough sets was proposed by replacing crisp binary relations with fuzzy relations by Dubois and Prade. In this paper, we introduce and investigate some properties of intuitionistic fuzzy rough approximation operators and intuitionistic fuzzy relations by means of topology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.579-587
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• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].