• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.147-152
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• 1985

The error-trapping decoder is constructed for the (7, 3) Reed-Solomon code. The syndrome resister is constructed with the encoder and the substanial test logic circuits. The element of GF(8) is represented by the triple D-flip-floops. The hardware is constructed. And it is controlled by the micro computer(Apple II). The time for the encoding and the decoding were $350\musecs and 910u secs respectively. The experimental results show that the two symbol errors were corrected and 4-bit-binary-burst errors were also corrected.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.943-952
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• 2018

This paper presents a new type of absolute rotary encoder system based on the affine n-digit N-ary gray code. A brief comparison of the existing encoder systems is carried out in terms of resolution, encoding and decoding principles and number of sensor heads needed. Using the proposed method, two different types of encoder disks are designed, namely, color-coded disk and grayscale coded disk. The designed coded disk pattern is used to manufacture 3 digit 3 ary and 2 digit 5 ary grayscale coded disks respectively. The manufactured disk is used with the light emitter and photodetector assembly to design the entire encode system. Experimental analysis is done on the designed prototype with LabVIEW platform for data acquisition. A comparison of the designed system is done with the traditional binary gray code encoder system in terms of resolution, disk diameter, number of tracks and data acquisition system. The resolution of the manufactured system is 3 times higher than the conventional system. Also, for a 5 digit 5 ary coded encoder system, a resolution approximately 100 times better than the conventional binary system can be achieved. In general, the proposed encoder system gives $(N/2)^n$ times better resolution compared with the traditional gray coded disk. The miniaturization in diameter of the coded disk can be achieved compared to the conventional binary systems.

• ETRI Journal
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• v.32 no.4
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• pp.588-595
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• 2010

This paper proposes encoding and decoding for nonlinear product codes and investigates the performance of nonlinear product codes. The proposed nonlinear product codes are constructed as N-dimensional product codes where the constituent codes are nonlinear binary codes derived from the linear codes over higher order alphabets, for example, Preparata or Kerdock codes. The performance and the complexity of the proposed construction are evaluated using the well-known nonlinear Nordstrom-Robinson code, which is presented in the generalized array code format with a low complexity trellis. The proposed construction shows the additional coding gain, reduced error floor, and lower implementation complexity. The (64, 24, 12) nonlinear binary product code has an effective gain of about 2.5 dB and 1 dB gain at a BER of $10^{-6}$ when compared to the (64, 15, 16) linear product code and the (64, 24, 10) linear product code, respectively. The (256, 64, 36) nonlinear binary product code composed of two Nordstrom-Robinson codes has an effective gain of about 0.7 dB at a BER of $10^{-5}$ when compared to the (256, 64, 25) linear product code composed of two (16, 8, 5) quasi-cyclic codes.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.45.6-45
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• 2002

In this paper, a novel optimization algorithm which searches for the local minima of a given cost function is proposed using the familiar property of a binary string, and is applied to the parametric identification of a continuous-time state equation by the estimation of system parameters as well as initial state values. A simple electrical circuit severs as an example, whose precise identification results show the superiority of the proposed algorithm.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.61-62
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• 2005

In this paper, we investigate the encoding and decoding method of turbo codes that offer a variety of coding rates from 1/3 to 6/7 in Digital Video Broadcast Return Channel via Satellite (DVB-RCS) standard to provide ship-internet service with high-quality.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.65-68
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• 2002

In an automatic fingerprint recognition system, a thinning process after binarization is commonly used. However it gives rise to spurs and holes often causing many spurious minutiae. Thus, more elaborate postprocessing is urgently needed to remove such spurious minutiae. To overcome this problem, we present a method of extracting minutiae based on horizontal and vertical run-length encoding from a binary fingerprint image without thinning process. Experimental results show that the proposed method for extracting minutiae is fairly reliable and fast, when il is compared to other method adopting a thinning process.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.1
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• pp.39-50
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• 2010

In this paper, we analyze and simulate the performance of a tactics mobile communication system based on ultra wide band (UWB) in multi-user interference (MUI) environments. This system adopts a double binary turbo code for forward error correction (FEC). Wireless channel is modeled a modified Saleh and Valenzuela (SV) model. We employ a space time block coding (STBC) scheme for enhancing system performance. System performance is evaluated in terms of bit error probability. From the simulation results, it is confirmed that the tactics mobile communication system based on UWB, which is encoded with the double binary turbo code, can achieve a remarkable coding gain with reasonable encoding and decoding complexity in multi-user interference environments. It is also known that the bit error probability performance of the tactics mobile communication system based on UWB can be substantially improved by increasing the number of iterations in the decoding process for a fixed cod rate. Besides, we can demonstrate that the double binary turbo coding scheme is very effective for increasing the number of simultaneous users for a given bit error probability requirement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.