• KIEE International Transaction on Systems and Control
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• 제12D권1호
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• pp.12-17
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• 2002

We propose a new category of neurofuzzy networks- Self-organizing Neural Networks(SONN) with fuzzy polynomial neurons(FPNs) and discuss a comprehensive design methodology supporting their development. Two kinds of SONN architectures, namely a basic SONN and a modified SONN architecture are dicussed. Each of them comes with two types such as the generic and the advanced type. SONN dwells on the ideas of fuzzy rule-based computing and neural networks. Simulation involves a series of synthetic as well as experimental data used across various neurofuzzy systems. A comparative analysis is included as well.

• Nonlinear Functional Analysis and Applications
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• 제28권3호
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• pp.731-751
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• 2023

If p(z) is a polynomial of degree n having all its zeros in |z| ≤ k, k ≥ 1, then for any complex number α with |α| ≥ k, and r ≥ 1, Aziz [1] proved $$\left{{\int}_{0}^{2{\pi}}\,{\left|1+k^ne^{i{\theta}}\right|^r}\,d{\theta}\right}^{\frac{1}{r}}\;{\max\limits_{{\mid}z{\mid}=1}}\,{\mid}p^{\prime}(z){\mid}\,{\geq}\,n\,\left{{\int}_{0}^{2{\pi}}\,{\left|p(e^{i{\theta}})\right|^r\,d{\theta}\right}^{\frac{1}{r}}.$$ In this paper, we obtain an improved extension of the above inequality into polar derivative. Further, we also extend an inequality on polar derivative recently proved by Rather et al. [20] into L^r-norm. Our results not only extend some known polynomial inequalities, but also reduce to some interesting results as particular cases.

• 한국측량학회지
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• 제21권2호
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• pp.165-172
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• 2003

IKONOS 위성영상은 지형·지물의 분포 파악 및 추출에 적합하여 많은 분야에서 이를 이용한 연구가 활발히 진행되고 있다. 그러나, IKONOS 위성영상은 3차원 지형정보를 추출할 수 있는 위성센서의 위치와 자세에 대한 정보를 공개하지 않고 있어 영상의 3차원 지형정보 획득을 위해서는 영상에서 제공하는 유일한 자료인 RPC(Rational Polynomial coefficients) 정보를 이용해야만 하는 실정이다. 이에 본 연구에서는 IKONOS 위성영상이 제공하는 RPC 정보를 통해 3차원 지상좌표 추출 알고리즘을 구현하여 프로그램을 개발하였으며, 이를 통한 3차원 지상좌표 추출시 발생하는 오차를 지상기준점 측량성과에 의해 보정하여 지상기준점의 수와 배치에 따른 위성영상의 기하학적 정확도 분석을 수행하므로써 고해상도 위성영상을 이용한 측정정확도 및 효율성을 향상시킬 수 있었다.

• Nonlinear Functional Analysis and Applications
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• 제27권2호
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• pp.323-329
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• 2022

Let $p(z)=\sum\limits_{\nu=0}^{n}a_{\nu}z^{\nu}$ be a polynomial of degree n and $p^{\prime}(z)$ its derivative. If $\max\limits_{{\mid}z{\mid}=r}{\mid}p(z){\mid}$ is denoted by M(p, r). If p(z) has all its zeros on |z| = k, k ≤ 1, then it was shown by Govil [3] that $$M(p^{\prime},\;1){\leq}\frac{n}{k^n+k^{n-1}}M(p,\;1)$$. In this paper, we first prove a result concerning the sth derivative where 1 ≤ s < n of the polynomial involving some of the co-efficients of the polynomial. Our result not only improves and generalizes the above inequality, but also gives a generalization to higher derivative of a result due to Dewan and Mir [2] in this direction. Further, a direct generalization of the above inequality for the sth derivative where 1 ≤ s < n is also proved.

• 대한수학회보
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• 제55권2호
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• pp.675-677
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• 2018

• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 추계학술발표회 논문집
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• pp.92-102
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• 1986

In this paper, Modular cell approach was applied to custom IC design or RS decoder. For the design of RS decoder by modular cells, 3 basic cells and one extra circuit are designed, these are, SYN cell for syndrome calculation, AL cell for error locator polynomial calculation, and REM cell for remaining error transform calculation. RS decoder design by these basic cells is very simple and regular, and naturally suitable for VLSI RS decoder design.

• Nonlinear Functional Analysis and Applications
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• 제26권2호
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• pp.331-345
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• 2021

Let p(z)be a polynomial of degree n. Then Bernstein's inequality [12,18] is $${\max\limits_{{\mid}z{\mid}=1}}\;{\mid}p^{\prime}(z){\mid}\;{\leq}\;n\;{\max_{{\mid}z{\mid}=1}{\mid}(z){\mid}}$$. For q > 0, we denote $${\parallel}p{\parallel}_q=\{{\frac{1}{2{\pi}}}{\normalsize\displaystyle\smashmargin{2}{\int\nolimits_{0}}^{2{\pi}}}\;{\mid}p(e^{i{\theta}}){\mid}^qd{\theta}\}^{\frac{1}{q}}$$, and a well-known fact from analysis [17] gives $${{\lim_{q{\rightarrow}{{\infty}}}}\{{\frac{1}{2{\pi}}}{\normalsize\displaystyle\smashmargin{2}{\int\nolimits_{0}}^{2{\pi}}}\;{\mid}p(e^{i{\theta}}){\mid}^qd{\theta}\}^{\frac{1}{q}}={\max\limits_{{\mid}z{\mid}=1}}\;{\mid}p(z){\mid}$$. Above Bernstein's inequality was extended by Zygmund [19] into L^q norm by proving ║p'║_q ≤ n║p║_q, q ≥ 1. Let p(z) = a₀ + ∑ⁿ_𝜈=𝜇 a_𝜈z^𝜈, 1 ≤ 𝜇 ≤ n, be a polynomial of degree n having no zero in |z| < k, k ≥ 1. Then for 0 < r ≤ R ≤ k, Aziz and Zargar [4] proved $${\max\limits_{{\mid}z{\mid}=R}}\;{\mid}p^{\prime}(z){\mid}\;{\leq}\;{\frac{nR^{{\mu}-1}(R^{\mu}+k^{\mu})^{{\frac{n}{\mu}}-1}}{(r^{\mu}+k^{\mu})^{\frac{n}{\mu}}}\;{\max\limits_{{\mid}z{\mid}=r}}\;{\mid}p(z){\mid}}$$. In this paper, we obtain the L^q version of the above inequality for q > 0. Further, we extend a result of Aziz and Shah [3] into L^q analogue for q > 0. Our results not only extend some known polynomial inequalities, but also reduce to some interesting results as particular cases.

• 한국정보통신학회논문지
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• 제14권3호
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• pp.628-636
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• 2010

본 논문에서는 GF($2^m$)상의 표준기저를 사용한 새로운 형태의 VCG에 의한 고속병렬 승산회로를 제안하였다. 승산기의 구성에 앞서, 피승수 다항식과 기약다항식의 승산을 병렬로 수행하는 벡터 코드 생성기(VCG) 기본 셀을 설계하였고, VCG 회로와 승수 다항식의 한 계수와 비트-병렬로 승산하여 결과를 생성하는 부분 승산결과 셀(PPC)를 설계하였다. 제안한 승산기는 VCG와 PPC를 연결하여 고속의 병렬 승산을 수행한다. VCG 기본 셀과 PPC는 각각 1개의 AND 게이트와 1개의 XOR 게이트로 구성된다. 이러한 과정을 확장하여 m에 대한 일반화된 회로의 설계를 보였으며, 간단한 형태의 승산회로 구성의 예를 GF($2^4$)를 통해 보였다. 또한 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였다. 본 논문에서 제안한 승산기는 VCG와 PPC을 반복적으로 연결하여 구성하므로, 차수 m이 매우 큰 유한체상의 두 다항식의 곱셈에서 확장이 용이하며, VLSI에 적합하다.

• Nuclear Engineering and Technology
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• 제55권4호
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• pp.1382-1399
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• 2023

Pressure relief valve (PRV) is one of the important control valves used in nuclear power plants, and its sealing performance is crucial to ensure the safety and function of the entire pressure system. For the sealing performance improving purpose, an explicit function that accounts for all design parameters and can accurately describe the relationship between the multi-design parameters and the seal performance is essential, which is also the challenge of the valve seal design and/or optimization work. On this basis, a surrogate model-based design optimization is carried out in this paper. To obtain the basic data required by the surrogate model, both the Finite Element Model (FEM) and the Computational Fluid Dynamics (CFD) based numerical models were successively established, and thereby both the contact stresses of valve static sealing and dynamic impact (between valve disk and nozzle) could be predicted. With these basic data, the polynomial chaos expansion (PCE) surrogate model which can not only be used for inputs-outputs relationship construction, but also produce the sensitivity of different design parameters were developed. Based on the PCE surrogate model, a new design scheme was obtained after optimization, in which the valve sealing stress is increased by 24.42% while keeping the maximum impact stress lower than 90% of the material allowable stress. The result confirms the ability and feasibility of the method proposed in this paper, and should also be suitable for performance design optimizations of control valves with similar structures.

• ETRI Journal
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• 제39권4호
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.