• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1093-1096
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• 1998

The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power $0.5\mu\textrm{m}$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1133-1138
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• 2018

Lightweight Encryption Algorithm (LEA) is one of the most promising lightweight block cipher algorithm due to its high efficiency and security level. There are many works on the efficient LEA implementation. However, many works missed the secure application services where the IoT platforms perform secure communications between heterogeneous IoT platforms. In order to establish the secure communication channel between them, the encryption should be performed in the on-the-fly method. In this paper, we present the LEA implementation performing the on-the-fly method over the ARM Cortex-M3 processors. The general purpose registers are fully utilized to retain the required variables for the key scheduling and encryption operations and the rotation operation is optimized away by using the barrel-shifter technique. Since the on-the-fly method does not store the round keys, the RAM requirements are minimized. The implementation is evaluated over the ARM Cortex-M3 processor and it only requires 34 cycles/byte.

• Journal of IKEEE
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• v.26 no.2
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• pp.226-231
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• 2022

The concept of information entropy has been widely applied in various fields. Recently, in the field of image processing, many technologies applying the concept of information entropy have been developed. As the importance and demand of computer vision technologies increase in modern industry, real-time processing must be possible in order for image processing technologies to be efficiently applied to modern industries. Extracting the entropy value of an image is difficult to process in real-time due to the complexity of computation in software, and a hardware structure of an image entropy filter capable of real-time processing has never been proposed. In this paper, we propose for the first time a hardware structure of a histogram-based entropy filter that can be processed in real time using a barrel shifter. The proposed hardware was designed using Verilog HDL, and Xilinx's xczu7ev-2ffvc1156 was set as the target device and FPGA was implemented. As a result of logic synthesis using the Xilinx Vivado program, it has a maximum operating frequency of 750.751 MHz in a 4K UHD high-resolution environment, and it processes more than 30 images per second and satisfies the real-time processing standard.

• Journal of IKEEE
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• v.24 no.3
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• pp.895-900
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• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.594-600
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• 2002

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.891-901
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• 2003

This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1117-1120
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• 1998

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.50-55
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• 2008

As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.