• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.961-963
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• 2009

a-Si process-based advanced-SPC (a-SPC) TFT has been developed and verified by manufacturing an AMOLED panel having improved cost competitiveness by using the existing a-Si infrastructure. The a-SPC TFT had superior device reliability and current drivability to a-Si TFT to meet the requirements of AMOLED backplane.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.133-136
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• 2007

IGZO TFTs were fabricated by conventional photolithography and wet-etching processes on metal substrates for the flexible display. The characteristics of TFTs on metal substrates were comparable to those of TFTs on glass substrates. Moreover, AM-OLED panels based on IGZO TFT arrays on metal substrates were successfully driven, for the first time.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.633-640
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• 2022

As service robots are applied to various fields, interest in an image processing processor that can perform an image processing algorithm quickly and accurately suitable for each task is increasing. This paper introduces an image processing processor design method applicable to robots. The proposed processor consists of an AGX board, FPGA board, LiDAR-Vision board, and Backplane board. It enables the operation of CPU, GPU, and FPGA. The proposed method is verified through simulation experiments.

• Polymer Science and Technology
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• v.18 no.2
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• pp.167-172
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• 2007

• The Magazine of the IEIE
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• v.35 no.8
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• pp.60-70
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• 2008

• Information Display
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• v.11 no.6
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• pp.2-11
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• 2010

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.8
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• pp.481-487
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• 2014

In this paper, we have proposed gigabit serial transceiver based on backplane architecture at the satellite communication digital transponder. The transponder supports the full combinational switching function with broadband multi-channel using programmable device - Xilinx space-grade Virtex-5 FPGA. In order to implement the switching function, GTX transceiver solution inside Virtex-5 FPGA is used. Also hardware implementation is simple because of no additional component. In order to use a GTX transceiver, signal integrity(SI) simulation of PCB design is essential. We investigate the characteristics of the S-parameter, eye diagram, channel jitter of GTX transmission line and conform that GTX Transceiver operates without error. Finally the proposed PCB design will be utilized at satellite communication digital transponder EQM-2(Engineering Qualification Model-2).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1056-1064
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• 2010

This paper presents the approximate analysis method for the symmetric transmission line crossing the aperture in an backplane. The method of moments is used to determine the aperture impedance for the construction of the equivalent transmission line that the aperture impedance apply to the transmission line as the shunt impedance. As the results, the insertion loss increases at the specific frequency range for the impedance matching. In the case of the mismatching, we are confirmed to the insertion gain at the specific frequency. Also the horizontal length of the aperture affects to the transmission line better than vertical length. The measurement of the insertion loss is performed to verify the theoretical analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.251-254
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• 1998

This paper suggests two data exchange protocols (DEPs) using shared memory. They support reliable data exchanges among components which are located in the same rack and use the same backplane bus and shared memory.