• Proceedings of the Korean Society for Bio-Environment Control Conference
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• 1999.04a
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• pp.24-29
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• 1999

포도 수확기를 개발하기 위해서는 포도 형상과 위치를 정확하게 파악하는 것이 필요하다. 신경회로망(Neural network)의 연상메모리(Associative memory)를 이용하여 포도 형상 정보를 인식하고자 한다. 신경회로망을 이용한 연상메모리는 학습 패턴(Learning pattern)을 학습한 후에 입력 패턴(Input pattern)으로부터 출력패턴을 얻는다. (중략)

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.409-412
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• 1997

In this paper, we propose a novel synthesis method of GBSB(Generalized BSB)-based neural autoassociative memories in which we analyze qualitative properties of GBSB model, recast a design problem of an associative memory to LMIP(Linear Matrix Inequality Problem), and optimize the LMIP using LMI techniques. The obtained memory satisfies many of the required properties of associative memories and has some peculiar properties. Comparing experimental results with those of others, we show its correctness and effectiveness.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1995.10b
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• pp.264-272
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• 1995

This paper presents an efficient design method to realize an associative memory with BSB neural networks by means of the parametrization of the solution space and searching for the optimal solution using an evolution program. In particular, the performance index based on DOA analysis in this paper may make and associative memory implementation to reach on the level of practical success.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.133-135
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• 2004

신경 회로망에서 연상 메모리(Associative Memory)는 주어진 자료에 대해 정보를 저장하고 복원하는 알고리즘이다. 본 논문에서는 학습된 영상의 정확한 분류와 왜곡된 영상의 복원 및 분류를 위해 기존의 퍼지 연상 메모리 알고리즘을 개선하였다. 기존의 퍼지 연상 메모리는 학습 데이터와 학습 원본과 같은 입력에 대해 우수한 복원 성능을 보이나 학습 데이터의 수가 증가할수록 그리고 왜곡된 입력에 대해 정확히 출력할 수 없고 복원 성능도 저하된다. 따라서 본 논문에서는 기존의 퍼지 연상 메모리 알고리즘을 개선하여 왜곡된 입력에 대해서도 원본 학습 데이터를 정확히 출력하고 복원하는 개선된 퍼지 연상 메모리 알고리즘을 제안하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.482-482
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• 2000

The essential requirements of neural network for human skill transfer are fast convergence, high storage capacity, and strong noise immunity. Bidirectional associative memory(BAM) suffering from low storage capacity and abundance of spurious memories is rarely used for skill transfer application though it has fast and wide association characteristics for visual data. This paper suggests generalization of classical BAM structure and new learning algorithm which uses supervised learning to guarantee perfect recall starting with correlation matrix. The generalization is validated to accelerate convergence speed, to increase storage capacity, to lessen spurious memories, to enhance noise immunity, and to enable multiple association using simulation work.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.4
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• pp.945-951
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• 2008

In this paper, a new high performance data cache scheme that improves exploitation of both the spatial and temporal locality is proposed. The proposed data cache consists of a hardware prefetch unit and two sub-caches such as a direct-mapped (DM) cache with a large block size and a fully associative buffer with a small block size. Spatial locality is exploited by fetching and storing large blocks into a direct mapped cache, and is enhanced by prefetching a neighboring block when a DM cache hit occurs. Temporal locality is exploited by storing small blocks from the DM cache in the fully associative buffer according to their activity in the DM cache when they are replaced. Experimental results on Spec2000 programs show that the proposed scheme can reduce the average miss ratio by $12.53%\sim23.62%$ and the AMAT by $14.67%\sim18.60%$ compared to the previous schemes such as direct mapped cache, 4-way set associative cache and SMI(selective mode intelligent) cache[8].

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.05a
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• pp.69-72
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• 2001

In this paper, we propose a new design method for bidirectional associative memories model with high error correction ratio. We extend the conventional GBAM model using bias terms and formulate a design procedure in the form of a constrained optimization problem. The constrained optimization problem is then transformed into a GEVP(generalized eigenvalue problem), which can be efficiently solved by recently developed interior point methods. The effectiveness of the proposed approach is illustrated by a example.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.7
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• pp.680-688
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• 2001

In this paper, we propose a reliable method for searching the optimally performing generalized brain-state-in-a-box (GBSB) neural associative memory using an evolution program (EP) given a set of prototype patterns to be stored as stable equilibrium points. First, we exploit some qualitative guidelines necessary to synthesize the GBSB model. Next, we parameterize the solution space utilizing the limited number of parameters to represent the solution space. Then, we recast the synthesis of GBSB neural associative memories as two constrained optimization problems, which are equivalent to finding a solution to the original synthesis problem. Finally, we employ an evolution program (EP), which enables us to find an optimal set of parameters related to the size of domains of attraction (DOA) for prototype patterns. The validity of this approach is illustrated by a design example and computer simulations.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.159-165
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• 1994

In this paper, we propose a multi-layer associative neural network structure suitable for hardware implementaion with the function of performance refinement and improved robutst capability. Unlike other methods which reduce network complexity by putting restrictions on synaptic weithts, we are imposing a requirement of hidden layer neurons for the function. The proposed network has synaptic weights obtainted by Hebbian rule between adjacent layer's memory patterns such as Kosko's BAM. This network can be extended to arbitary multi-layer network trainable with Genetic algorithm for getting hidden layer memory patterns starting with initial random binary patterns. Learning is done to minimize newly defined network error. The newly defined error is composed of the errors at input, hidden, and output layers. After learning, we have bidirectional recall process for performance improvement of the network with one-shot recall. Experimental results carried out on pattern recognition problems demonstrate its performace according to the parameter which represets relative significance of the hidden layer error over the sum of input and output layer errors, show that the proposed model has much better performance than that of Kosko's bidirectional associative memory (BAM), and show the performance increment due to the bidirectionality in recall process.