• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.46-51
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• 2015

In this paper, I design a linear array antenna simulator for anti-jamming GPS systems and perform various performance analysis by simulation. First, I generate simulated transmission signals through the analysis of GPS satellite signal structure, and analyze SNR(Signal to Noise power Ratio) performance of linear array antenna according to number of arrays under noise environments. In addition, I analyze the performance of the anti-jamming beam pattern using MMSE(Minimum Mean Square Error) signal processing method, and also analyze the anti-jamming performance considering antenna calibration problem when there are different delays between arrays.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.49-52
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• 2003

Two types of ozone monitors using UV absorption method were tried in consideration of cost of the monitor and precision in measuring. The high concentration ozone monitor for high concentration real time ozone monitoring from ozone generator was composed of a low pressure mercury lamp as UV source, a photo multiplier tube as UV detector and signal processing unit for the most part. This structure could be very useful for low price high concentration ozone monitor due to simple system structure and fairly good monitoring characteristics. The developed system showed good linear output characteristics to ozone in the measuring concentration range of 0.05 and 2 wt.%. For accuracy ambient ozone monitoring in ambient in ppm level, the system composed of a high power pulsed xenon lamp as UV source, an optical spectrometer with a high sensitivity linear CCD array as UV detector and signal processing unit in brief speaking was proposed our study for the first time in the world. The developed system showed good linearity and sensitivity in relative low measuring range between 10ppm and 10,000ppm, and showed some feasibility of high resolution ozone monitor using CCD array as photodetector.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.57-58
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• 2005

Recently the telematics system is used widely. Users want to high quality communications. Since the primary advantage of using an array is to enhance a desired signal and reject jamming interferences, array signal processing is essential to satisfy unmet demand of user. In general, beamforming is a spatial filtering operation performed on the data received by an array of sensors. So we propose the beamformer design that use FPGA for real time processing. And we use zero-padding interpolation for high resolution data.

• The Journal of the Convergence on Culture Technology
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• v.9 no.5
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• pp.517-522
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• 2023

Existing radars have been developed by applying RF sub-array algorithms, and recently, fully digital Multiple-Input Multiple-Output (MIMO) radar algorithms have been implemented for vehicle radars. In this paper, the radar algorithm applying the Phased MIMO method to the hardware of the RF sub-array method, which is an unsecured technology, was implemented and verified in real time. In order to secure RF sub-array Phased MIMO algorithm technology, a hardware structure for FPGA-based real-time signal processing was presented, and performance was first predicted through design and simulation. Through this, the digital signal of FPGA-based broadband MIMO FMCW radar The processing hardware was developed, and the Phased MIMO radar algorithm of the RF sub-Array method was finally implemented and verified in real time. Based on this, it is judged that it will be possible to secure and apply core technologies necessary for terahertz band radar in the future.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.4
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• pp.43-49
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• 2021

A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.

• Journal of Satellite, Information and Communications
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• v.12 no.2
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• pp.65-70
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• 2017

The structure of MMSE receiver front-ended by CMA(Constant Modulus Array) array working in CDMA forward link which is applicable to LEO spread spectrum satellite communication system is proposed. By using the despreaded pilot signal of forward link as a reference signal, the CMA array can capture multi-path signals securely even in severely faded LEO satellite channel. The remaining MAI (Multiple Access Interference) is cancelled by the cascaded MMSE receiver. Besides theoretical development, through relevant computer simulation, it is proved that the proposed system shows much better BER performance than any other possible candidate systems. As a spatio-temporal receiver mounted on a mobile vehicle, the proposed system also reduces implemental cost and complexity by adopting the simplest algorithm for its spatial and temporal domain processing.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.2
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• pp.1-6
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• 2005

Ryu et al. proposed a multiple target DOA tracking algorithm using a linear sensor array. In Ryu's algorithm first, the signal subspace is estimated using sensor output and the angular innovations of targets are extracted from the estimated signal subspace. Next, the DOA's of targets are tracked using the angular innovations as the inputs of Kalman filters. Ryu's algorithm has good features that it has no data association problem and is efficient. However, Ryu's algorithm can't be a lied to an arbitrarily shaped array because it was proposed using linear sensor array. Actually, when the sensor array is used in the various application fields, sensors have a position error. Therefore, the sensor array can be an arbitrarily shaped array. In this paper, we propose a multiple target DOA tracking algorithm applicable to an arbitrarily shaped array, and it sustains the good features of Ryu's algorithm.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.61-63
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• 1987

In this paper, we develope a system which can perform signal processing for bar-code laser scanner. This system is composed of optical detector and preprocessor. The former detects the diffused light and converts it into TTL lebel output. The latter discriminator valid data from various raw data and transmits data to micro-processor. The preprocessor consists of edge transition detector, latch signal generator, module counter, register array, adder array, and buffer memory control circuit etc..

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.