• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.9
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• pp.62-69
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• 1996

In this paper, the bit-level 1-dimensional systolic array for modular multiplication is designed. First of all, the parallel algorithm and data dependence graph from walter's method based on montgomery algorithm suitable for array design for modular multiplication is derived. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays are obtained and then are evaluated by various criteria. As it is modified the array which is derived form [0,1] projection direction by adding a control logic and it is serialized the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for expansile module and it is easy for fault tolerance due to unidirectional paths. It is suitable for RSA cryptosystem which deals iwth the large size and many consecutive message blocks.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.2 s.314
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• pp.39-45
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• 2007

This paper presents a novel scheme that quickly searches for the sweet spot of multiple array antennas, and locks on to it for high-speed millimeter wavelength transmissions, when communications to another antenna array are disconnected. The proposed method utilizes a modified genetic algorithm, which selects a superior initial group through preprocessing in order to solve the local solution in agenetic algorithm. TDD (Time Division Duplex) is utilized as the transfer method and data controller for the antenna. Once the initial communication is completed for the specific number of individuals, no longer antenna's data will be transmitted until each station processes GA in order to produce the next generation. After reproduction, individuals of the next generation become the data, and communication between each station is made again. Simulation results of 1:1, 1:2, 1:5 array antennas confirmed the efficiency of the proposed method. The 16bit split is 8bit, but it has similar performance as 16bit gene.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• The Journal of the Korea Contents Association
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• v.12 no.6
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• pp.1-8
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• 2012

According that most integral imaging techniques have used rectangular lens array, this integrated distribution of light is recorded in the form of a rectangular grid. However, hexagonal lens array gives a more accurate approximation of ideal circular lens and provides higher pickup/display density than rectangular lens array[4]. Using the parallel processing technique in order to generate the elemental imaging for hexagonal lens array, each pixel that compose the elemental imaging should be determined to belong to the hexagonal lens. This process is output to the screen for every pixel in progress, and many computations are required. In this paper, we have proposed parallel processing method using an OpenCL to generate the elemental imaging for hexagonal lens array in 3D volume date. In the experimental result of proposed method show speed of 20~60 fps for hexagonal lens array of $20{\times}20$ sizes and input data of Male[$128{\times}256{\times}256$] volume data.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.811-820
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• 1997

Disk arrays are using to enhance data trandfer rate and I/O performance in multimedia applications which need a high-performance storage device with large storage capacity and high-speed network.As performance varies with configuration and data layout scheme,disk array characteristic variables must be approrpriately deter-mined in desibning disk array archetecture for a speciffic applicatoin. In this paper,in order to design a disk array architecturte as a storage server of a small-scale VOD system,we evaluate performance of a disk array to chose the number of disks in the array,disk array cinfiguration,a degree of declustering for a given data block size of continous media file system and I/D request size through simulation.Simulation result shows that RAID level 5 with 5 disks ios a suitable candidate for the disk array architecture which privides MPEG-2 files with a rate of 6 Mbps,Moreover,we whow that stripe unit is 64 KB and a layout scheme is contigous placement.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.217-224
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• 2009

Most divide-and-conquer implementations for Delaunay triangulation utilize quad-edge or winged-edge data structure since triangles are frequently deleted and created during the merge process. How-ever, the proposed divide-and-conquer algorithm utilizes the array based data structure that is much simpler than the quad-edge data structure and requires less memory allocation. The proposed algorithm has two important features. Firstly, the information of space partitioning is represented as a permutation vector sequence in a vertices array, thus no additional data is required for the space partitioning. The permutation vector represents adaptively divided regions in two dimensions. The two-dimensional partitioning of the space is more efficient than one-dimensional partitioning in the merge process. Secondly, there is no deletion of edge in merge process and thus no bookkeeping of complex intermediate state for topology change is necessary. The algorithm is described in a compact manner with the proposed data structures and operators so that it can be easily implemented with computational efficiency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.220-227
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• 2002

An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.

• Proceedings of the Acoustical Society of Korea Conference
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• 1997.06a
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• pp.68-74
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• 1997

Ship radiated noise is an infortant parameter which dtermines Anti Submarine Warfare(ASW) countermeansure or passive Sonar detection and classification performance. Its measurement should be performed under controlled ocean acoustic environment. In data reduction of the measured data from hydrophone array, theeffect fo ambient noise, surface reflection and bottom reflection etc. should be compensated to obtain the source level of the ship radiated noise. This study describes the measurement hydrophone array design criteria based on the analysis of transimission anomaly due to the surface reflection.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.