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(Design of Systolic Away for High-Speed Fractal Image Compression by Data Reusing)  

U, Jong-Ho (부경대학교 전자컴퓨터정보·통신공학부)
Lee, Hui-Jin (부경대학교 전자컴퓨터정보·통신공학부)
Lee, Su-Jin (부경대학교 전자컴퓨터정보·통신공학부)
Seong, Gil-Yeong (경상대학교 정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.3, 2002 , pp. 220-227 More about this Journal
Abstract
An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.
Keywords
프랙탈영상압축;시간공간사상;시스토릭 어레이;VLSI 어레이;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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