• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.631-632
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• 2006

In this paper, acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.24-29
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• 1983

In this paper, a floating-point processor which satisfied the subset of the proposed IEEE standard has been designed and realized by TTL chips. This processor consists of a floating-point arithmetic unit and a control sequencer. AHPL has been used in the design of sequencer. The execution times for the arithmetic operations were measured and compared with other microprocessor. The results had shown faster operations compared to the Z-80 processor. Though this processor was built by TTL chips, it could be fabricated as a one-chip processor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.147-155
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• 1989

In this paper, a real-time implementation of the TWS(track-while-scan) system using the high-speed DSP (digital signal processor) TMS320C25 is described. First, attempts have been made to investigate the FWL (finite word length) effect, which is caused by employing a fixed point arithmetic, of implementing the Kalman filter. The real-time TWS system consists of TWS arithmetic unit, scan converter, and system controller. In addition, the TWS system is in tegrated in the Multi-Bus. In experiment, it is observed that by employing the floating point arithmetic the computation time of 0.35sec is required for tracking 8 targets simultaneously, while 0.28sec is required for the fixed point arithmetic. Since the TWS system is designed to track up to 8 targets simultaneously, we conclude that the system is enough to process Kalman filter in a real-time.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.101-108
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• 2017

As the quantum gate matrix is a $r^{n+1}{\times}r^{n+1}$ dimension when the radix is r, the number of control state vectors is n, and the number of target state vectors is one, the matrix dimension with increasing n is exponentially increasing. If the number of control state vectors is $2^n$, then the number of $2^n-1$ unit matrix operations preserves the output from the input, and only one can be performed the unitary operation to the target state vector. Therefore, this paper proposes a new method of function embedding that can replace $2^n-1$ times of unit matrix operations with deterministic contribution to matrix dimension by arithmetic power switch of the unitary gate. The proposed function embedding method uses a binary literal switch with a multivalued threshold, so that a general purpose hybrid MCU gate can be realized in a $r{\times}r$ unitary matrix.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.108-115
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• 1990

This paper describes the design and fabrication of a processing element that will be used as a component in the construction of a two dimensional systolic for FFT. The chip performs data shuffling and radix-2 decimation-in-time (DIT) butterfly arithmetic. It consists of a data routing unit, internal control logic and HBA unit which computes butterfly arithmetic. The 6.5K transistors processing element designed with standard cells has been fabricated with a 2u'm double metal CMOS process, and evaluated by wafer probing measurements. The measured characteristics show that a HBA can be computed in 0.5 usec with a 20MHz clok, and it is estimated that the FFT of length 1024 can be transformed in 11.2 usec.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.5
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• pp.636-642
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• 1999

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

• Journal of Korea Water Resources Association
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• v.40 no.2 s.175
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• pp.159-170
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• 2007

This study evaluated the parameters of Clark unit hydrograph (UH) estimated using the rainfall-runoff measurements and evaluated their variability. This also includes the quantification of basin and meteorological factors using probability density functions, selection of storm events with mean affecting factors, and derivation of average parameters of the Clark UH from storm events selected. Summarizing the results from this procedure are as follows. (1) It is not easy to avoid much uncertainty on the decision of runoff characteristics (that is, the concentration time and storage coefficient) even with some rainfall-runoff events are available. (2) As the distribution function of concentration time is very skewed, a simple arithmetic mean may lead a biased estimate. That is, the arithmetic mean based on the normal distribution can not be representative anymore. The mode may well be the representative in this case. On the other hand, the storage coefficient shows a symmetric distribution function, so the arithmetic mean may be used use for its representative. For the basin in this study, the concentration time in this study is estimated to be about 7 hours, and the storage coefficient about 22 hours.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.141-143
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• 2002

We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.